AMD Goes Hybrid: Zen 4 + Zen 4c in Mobile
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One of my start-of-2023 predictions was that AMD would resist the urge to go hybrid with its core designs. What this means is that I predicted that AMD would not be tempted to combine performance cores and efficiency cores into the same product. I made this prediction for multiple reasons.
First, typically when you build two types of cores, it helps if they’re co-optimized for each other in the first place - Zen 4c was primarily built for Bergamo, the server hardware, so to see it in a consumer chip felt very odd. Zen 4c as a chip carries exactly the same performance profile, latencies, IPC, but targets a much lower clock optimization level, around 3 GHz, whereas Zen 4 can go above 5.5 GHz. Having lots of Zen 4c cores, up to 128, in server platforms makes sense where performance per socket matters, and you save 35% die area with the Zen 4c design. The other thing is that Zen 4c is almost identical except for the L3 cache, which is 1 MB/core rather than 2 MB/core.
Second, with great hybrid power comes great hybrid responsibility - Intel leverages a strong relationship with Microsoft on the Windows scheduler and uses technologies such as Thread Director to ensure that workloads end up on the right cores. Aside from Zen 1 issues with NUMA, AMD hasn’t broached the subject yet of working with Microsoft on adequate scheduling in a hybrid design, so I’d be expecting a bigger launch with that as part of the messaging.
Third, and perhaps most importantly, I expected it to be more of a Zen 5 generation thing. Enabling a hybrid design typically brings benefits up and down the stack when done right, so to introduce it mid-cycle with the Zen 4 generation felt off.
However, if AMD has shown anything of late, it’s that it likes to trial out things first before enabling a technology across the product stack. We’re seeing it with the Ryzen AI embedded engines, only found on 7040 series mobile products today - it’s not full stack yet, but it will come next generation.
And so today’s news is that AMD is launching three new SKUs with a hybrid design, combining Zen 4 and Zen 4c cores into a single chip, which has the codename of ‘Phoenix 2’. These are mid-to-low end mobile processors, with the focus on offering something with perhaps lower power when in low-end workloads.
In the current product stack, AMD has a Ryzen 5 7540U, which is a 6 core Zen4 design. This is a mid-range mobile processor, not exactly setting the world alight but is a workhorse of good mid-priced laptops.
This SKU will be replaced with two. The Ryzen 5 7545U, still a six core processor but with two Zen 4 cores and four Zen 4c cores. The frequencies of the main cores are still the same, and it has the same graphics, the same feature set. While AMD hasn’t disclosed the frequencies of the Zen 4c cores, given the design point in the enterprise silicon, I expect ~3.1 GHz.
There will also be a Ryzen 3 7440U - a quad core processor, with a 1 Zen 4 + 3 Zen4c design. The third SKU will be a revised Z1, which we see in some of the cheaper AMD-based handheld console-like computers today.
This is the main graph that correlates full system performance at a given power level. The orange bar is the more traditional six Zen 4 core processor (which is itself a cut-down 8-core design, whereas the red is the one with four Zen 4c cores. The performance at lower power is higher, with the trade-off at higher power, it doesn’t chew though the workload as fast. Honestly, these numbers are somewhat negligible as these lines are so close, and the key factor here is going to be background idle power.
As these Zen 4c cores are more efficient at lower power and frequencies, the goal here is to put workloads on them that aren’t performance sensitive and you enjoy the energy efficiency of that core. Really it’s the basis of any hybrid CPU design, either from smartphones or notebooks.
In order to realise this, there has to be a way for the operating system to recognize different cores, and schedule workloads appropriately. This is a very hard thing™ to do - the OS doesn’t often know if a workload is latency sensitive until it can analyse it, which takes work, and as to which core it needs to sit on as time progresses. It also depends if the device is on power or battery, or in performance mode, or is reliant on things such as networking. The base Windows does ‘an ok job’, though it’s clear from other hybrid windows designs from Intel and Qualcomm that it isn’t as simple as simply ‘having’ a hybrid design. Intel has beaten the drum about its proprietary Thread Director layer, which allows the CPU to give the OS hints on where to put workloads - speaking with the fellows about how this needs to be configured and you can see them get grey hair and age in real time, because it’s not a trivial matter. AMD in this instance isn’t saying much, if anything, about what they’ve done to work towards this issue, which is a lingering question mark. I’ve reached out with questions, and I’m waiting to hear back.
AMD didn’t include any partner commentary or design wins yet on these chips, however I expect that come January and the CES event, there might be some on display. The bottom line is that this feels like a trial run for something bigger next generation.
If we look at market growth and strategy, while this new chip allows AMD to address more of the bottom end of the market, for example education, it’s worth noting that the bottom end of the market often has the lower margins, even at volume, and we have to be blunt here because AMD has gone out of its way to design and manufacture a whole new SoC for a limited number of SKUs. Sure there’s some give from the chips already designed, but there’s still a significant amount of NRE (non-recurring engineering) costs that go into designing a full new piece of silicon. The value therefore in this chip isn’t going to be the revenue, but the practical learnings from having a hybrid design at retail before a bigger push into hybrid with the next generation.