The modern foundry now regularly puts on a variety of events for customers and partners (and sometimes the media). In the past these have been behind closed doors, however there is a push to make them the site of announcements highlighting the future of the specialist or leading edge technologies. Within the scope of a week, I attended events from GlobalFoundries, Intel, and TSMC all in the EU, with Samsung having their event a couple of weeks later (in the same hotel as the GF event in Munich, but my application to Samsung to attend was denied). The key messages from these events start with 'we're open for business', and end with 'look how successful we are'. It's a good strategy, especially in a very R&D driven industry looking to develop the latest technologies, whether that's new transistor types, increasing tolerances on higher density memory or faster logic, or enabling technologies like specialist memory in smaller and smaller process nodes. Then there's the automotive angle, or the RF angle, or the high-voltage angle, leading up where the battleground for the next generation of high performance silicon will be fought: advanced packaging.
I have published interviews with GlobalFoundries' CEO Dr. Tom Caulfield and Intel's EVP and GM of Technology Development Dr. Ann Kelleher. For TSMC's event, or more specifically the US event the week prior, they commissioned a video from me to briefly explain their new event, the OIP Forum, with their two leading groups around packaging: the 3DFabric Alliance and the 3Dblox 2.0 standards. It's a short 7 minutes highlighting the importance of having standards bodies around these new technologies such that everyone can beat to the same drum, rather than it being a complicated mess of unique solutions.
The take home of the video is to attend the OIP events occurring worldwide, and I went along to the one in Amsterdam for EU partners and customers. This post isn't sponsored, but I wanted to share a few items regarding TSMC's process node developments disclosed/clarified at the event.
Fabs
Starting off with the numbers we already know from the quarterly financial calls: TSMC builds the equivalent of 11-12 million 12-inch wafers every year. The revenue is now 50% or greater (53% in 23Q2) on its two leading edge node technologies: 7nm and 5nm, with revenue for 3nm coming through by the end of the year, and those nodes count for around 20% of the wafer volume. By platform, around 44% of the revenue overall comes from HPC, 33% from smartphone, and the rest is split between IoT, Automotive, and everything else.
In terms of TSMC's production. It has four gigafabs in Taiwan, focusing squarely on 12-inch production. These gigafabs are built of separate phases, of which TSMC has increased its rate of building new phases from 2-per-year to 5-per-year since 2020. Alongside the gigafabs is APF6, or Advanced Packaging Fab 6, which opened in June 2023. We'll cover the technology in a bit, but TSMC's N3 volume comes from phases 5, 6, and 8 of Fab 18 in Tainan, and TSMC's future N2 is going into new fabs: Fab 20 in Hsinchu, and a new site in Taichung. In the past two years, TSMC has started construction on 10 phases - 5 in Taiwan for manufacturing, 2 in Taiwan for advanced packaging, and 3 overseas. TSMC's overseas operations include a fab in Nanjing (Fab 16) open since 2018, a new fab in Kumamoto Japan (Fab 23), and two new fabs in Arizona (Fab 21). The first Arizona location has started receiving tools, with the view to enable N4 volume production in 2024. The second fab in Arizona is under construction, and being built for N3. Combined, Arizona is aiming for 600k wafers per year, or 50k wafer starts per month - historically a gigafab is 100k+ a month, so Arizona right now is half a Gigafab. In Japan, the Kumamoto fab has started production with a view to volume in 2024 for 16/12nm and 28nm specialty technologies currently in high demand. TSMC also states that a new Chinese site began volume production in 2022 for 28nm technology. As part of the process, TSMC is already integrating machine learning into its production flow, to maintain quality and consistency, but also to optimize customer yield and production.
TSMC N3, N3E, N3P, N3X
But what you're really here for is the breakdown of how TSMC's N3 is going to perform. There have been a lot of reports that because TSMC decided to stick with FinFET technology with N3, that reports state that TSMC hasn’t been able to extract performance, as well as some of the delays. Here's what TSMC told us about their technology.
Firstly, on yields - today's N3 has the same defect density (D0) as N5 did at this current stage of development and production, and TSMC states they have 'industry leading' yield in high volume production. They expect N3 defect rates to track with N5 as expected and reach parity in due course. Note that N5 defect rates run to around 0.07 per cm2 (or 40-45 per wafer).
Here's what the roadmap looks like:
There are a lot of numbers to pack in here, but I'll go through them with you. All these numbers are referencing an example Arm Cortex-A715 core, one of the latest core designs.
At the top level:
From N5 to N3E, TSMC states N3E offers +18% speed (frequency), 30-60% density depending on SoC vs logic, and a 32% reduction in power.
N4PRF, a radio frequency optimized version of N4, is due for risk production in the second half of 2023/early 2024.
Then for 3nm:
N3 entered volume production in Q4 2022
N3E similarly enters volume production in Q4 2023, with a +5% speed increase with no change to density. N3E has passed performance and yield targets.
N3P will follow N3E, for production in 2H 2024. Compared to N3 (not N3E), N3P offers +10% frequency and a +4% increase in density compared to N3 (not N3E)
N3X is a higher performance version, for production in 2025. Compared to the standard N3, it offers +15% speed and +4% density for the same power.
As it stands, almost all the IP for N3E is ready and silicon proven, with UCIe and HBM3 being the last two major parts to complete (but has pre-silicon support today). N3P IP by contrast is mostly still pre-silicon support or still in development/planning.
TSMC will also develop automotive grade versions of N3 - normally TSMC would wait for 1m wafers of the main process before creating an automotive grade version, which creates a 2-3 year lag, but in this case the demand is high enough that TSMC will create N3AE, Automotive Early, in order to assist customers with designs earlier in the cycle than usual. N3A, the full version, will then come in 2026. TSMC stated that they see N3AE more of a consumer level version, whereas N3A will be full fat for enterprise deployment.
TSMC N2, N2X, N2P, BSPDN
Now we move onto TSMC's roadmap for N2, the process node using Gate-All-Around transistors.
Using a Cortex A715 as a base design, TSMC are claiming against an N3E node 5-15% speed improvements, better than 15% density, and about 25-30% power reduction. The numbers in the diagram convert that to a comparison against the base N3, just for consistency, but these numbers are likely to be either/or, rather than combined. The tough part of building these new transistors is actually the consistency of the transistor itself, according to a source of mine, and so TSMC are taking time to get it right it seems. TSMC is stating that a large part of the power decrease with N2 is the lower minimum voltage their design affords, which should scale into the current demand for high-efficiency hardware. The timeline for N2 involves risk production in 2025, leading to volume ramp in the second half of the year.
On the EDA side for N2, TSMC is stating that all the major EDA tools and vendors are certified ready. This includes a full EDA stack from Synopsys (while collaborating with Ansys for EMIR), an almost complete stack from Cadence (has EMIR, not Tx STA), and simulators from Synopsys, Cadence, and Siemens.
Also on the performance numbers - it's stated that the comparison was to an A715. For N3, TSMC introduced a new design model called FinFlex, allowing transistors to use a different amount of gates for high performance (known as 3-2) or high density (2-1) designs. The high-performance design allowed for higher frequency but cost power, whereas the high density allowed for more compact designs but couldn't be pushed as much. The idea is that modern HPC cores, like x86 or Arm cores, would use the performance transistors, whereas IO and efficiency cores might use the dense transistors. It looks like N2 won't have a FinFlex offering just yet, but in comparisons of the two transistor types to the standard N2 offerings, N2 gave 30% less power at iso frequency, or 13% frequency at iso-power. This goes in line with numbers they've reported, however TSMC offered more flavor to those numbers. At the event they did flash slides up with full voltage/power curve comparisons, however we weren't allowed to take pictures and these were the numbers I wrote down at the time. But it's good to see a level of consistency.
It's worth noting that TSMC's regular N2 process node will not feature a technology called backside power delivery, known as BSPDN. This is a technology that changes how the chip is built - instead of intertwining both power connections and signal connections above the transistors, the two types of connections are split - power on the backside, and signals on the front side. This is a complicated technique, and as a result TSMC will offer a version of N2 with BSPDN later in the cycle - approximately six months later compared to the standard N2. The benefits of BSPDN include simpler design rules, but increases in density (+10% over regular N2) and speed (+5-10%). Power is a bit harder to judge it seems, as one of the tradeoffs of better efficiency is either lower power or higher performance, and it seems TSMC is focusing on the performance aspects of BSPDN, especially due to less power signal/data signal crosstalk. We've seen something similar with TSMC's Wafer-on-Wafer technology - Graphcore used WoW on N7 to migrate some of their MIM capacitors from upper layers of the metal stack into a separate chip, making them larger and less susceptible to interference. The end result was better efficiency, which was used to crank up the frequency for a reported +30% increase in performance. BSPDN is more complex because it puts ALL the power on the backside, but not as substantial a change as WoW, so the benefits might be subdued. N2 + BSPDN doesn't seem to be given a specific name yet compared to other nodes, so we'll see if that changes closer to time.
To draw a parallel here - TSMC offering N2 and N2+BSPDN as different variants is going to be the industry norm. Intel has made it clear that for their version of BSPDN, which they're calling PowerVia, this will also be an optional extra for customers on their 20A/18A nodes. It has gone somewhat underreported, however because BSPDN is a lot more involved, it seems both companies will have to have BSPDN and non-BSPDN versions to satisfy all cost models and design choices.
Beyond TSMC N2
For TSMC beyond N2 and N2+BSPDN, the company has spoken about N2P and N2X, however few details have been provided. We expect these node variants to follow the same path as N3P and N3X relative to how those are minor speed or density increases. Beyond the N2 family, TSMC is still in research, however the typical improvements are likely to come over the next decade: Forksheets (a GAA variant for density improvements), CFET (also a GAA variant for major density, however perhaps at performance costs), 2D transistors, and other potential technologies like carbon nanotubes. Now we're talking more 2035+ timeframe.
High Bandwidth Memory
TSMC's event also focused on other technologies, such as memory, as part of the 3DFabric Memory Alliance. TSMC has monthly group meetings with all vendors to ensure alignment with roadmaps and packaging capabilities, as well as making sure that JEDEC and everyone is in alignment. The focus at the event was for HBM3 and HBM4. Here's what TSMC had to say about each partner.
JEDEC: HBM4 spec alignment with 16Hi stacks
Micron: HBM3 Gen2 product announced at 9.2 Gbps, also CoWoS silicon validation
Samsung: HBM3 12Hi collaboration for +50% capacity, also Buffer-less HBM study in progress
SK Hynix: HBM3 + HBM4 CoWoS collaboration, DTCO on HBM4, going beyond JEDEC spec, also UCIe HBM PHY
According to this list, SK Hynix seems further along with HBM4, however both Micron and Samsung are looking at higher capacity or higher bandwidth HBM3. With the demand for fast, high capacity HBM going through the roof, I'm sure most companies will take anything - but it's a case of manufacturability, supply chain, and consistency. HBM4 use the same frequencies as HBM3, but has double the pins for double bandwidth, so with any luck it should be a 'simpler' migration.
Analog Migration
On the analog side of manufacturing, TSMC is also expanding the toolkits of standard cells. TSMC previously announced ADM 1.0, for Analog Design Migration - what used to require full custom designs, TSMC offers a way to bring analog standard cells for N5 and N3. This now expands into ADM2.0, providing standard cells back to N16, and forward to N2. The goal is to continue back all the way to N28 and N40, to allow for wider customer adoption and a shorter time to market. There's also an eye to bring this to N2+BSPDN. Both Cadence and Synopsys offer full EDA support in schematic migration, circuit optimization, and layout migration.
3DFabric
A big part of the event was TSMC's 3DFabric Alliance, along with the 3Dblox packaging side. The goal here is to provide a common scalable set of design languages for customers that interface with common integration tools from the EDA vendors to allow for a flexible intregration of the next generation of expensive chips and the complicated packaging those chips need. By offering a unified set of design languages that the EDA systems can use for the development and simulation, the goal here is to reduce end-to-end costs for getting a chip to market, as well as accelerating that time to market. 3DFabric comes as a kit, with documentation, design flows, and technology files - one kit for each of TSMC's 8 packaging technologies. In case you're not up to speed, these fall into three buckets:
Integrated Fan Out (InFO): InFO_oS, InFO_LSI
Chip on Wafer on Substrate (CoWoS): CoWoS-S, CoWoS-L, CoWoS-R
System on Integrated Circuit (SoIC): SoIC-X, SoIC-P
This order is actually great - the ones at the top were first to market for TSMC overall, but also the InFO options are also almost complete from a 3DFabric Kit standard. The kits contain elements such as DRM, DRC, RCX, CAD, PERC, EMIR etc, and for InFO that is almost all complete for both variants. CoWoS-S is almost complete too, however L and R still have some progress. SoIC-X is about half done, whereas SoIC-P is just getting started. As always with these things, it simply takes time.
The other mentions at the event were two fold: TSMC is really pleased with the work they've done with AMD on the MI300. It uses multiple new techniques developed in partnership, but TSMC also confirmed that MI300 quadrants feature base die, of which two quadrants are mirrored. On each of these quadrant base die sit either two graphics chiplets or three CPU chiplets (this part we knew), but TSMC is heralding it as an unprecedented feat of 3D silicon integration. AMD's MI300 event is on December 6th, hopefully TSMC will be there to talk about it. The other mention at the event was an expansion of TSMC's university program - most foundries offer multi-project wafer programs for students and research groups to build test chips, and now TSMC is expanding his to include N16 and N7, with the PDKs available through imec.
And that wraps up TSMC OIP. I'm really glad they're opening it up to those of us that do external reporting. Right now we're only allowed in the first session on the first day, we can't take photos, and the slides go by really fast, but I'm hoping it moves to a more open event such as the other foundry players.