Tenstorrent Extends Japan Engagement
Training Engineers for 2nm RISC-V and AI
One of the finer treasure maps that AI startups have to guide themselves through is platform adoption. There are several options here - either (a) focus on clients that are buying the hardware and optimize it specifically for them, or (b) open source everything and encourage everyone to use it. Most startups, and especially most of the big ones, right now are selecting (a) - they work with key clients because they need to drive revenue. In order to go down the (b) open source route requires a good line of sight into the future, with the hope of capturing business later down the line.
Tenstorrent has been on the (b) strategy for a while. It started with having a strategy around both selling hardware and IP, then open sourcing the software stacks so people could look into it, then offering developer kits so even if you were not a lead customer, there was scope to test the design without signing an NDA. On top of this, the company also went out and signed large MOUs with clients, particularly in Asia - LG, Hyundai, and Samsung have all announced collaborations with Tenstorrent IP for their future SoCs in what could be multi-million dollar deals. Plus those are only the ones that have gone public so far.
On top of this, Tenstorrent has developed a relationship with Rapidus - a Japanese effort to enable leading edge manufacturing on home soil. Rapidus is in the process of building a fab in Hokkaido, which currently sits at 80% complete - the first EUV tools are expected to be installed in the next few months. The fab is starting with IBM’s 2nm development IP, and scaling it up into a fully fledged process. One of the first high volume parts in the fab will be an ASIC built using Tenstorrent IP.
The research and development arm connected to the fab is the LSTC, or the Leading-edge Semiconductor Technology Center, who are designing the ASIC with Tenstorrent IP.
In news today, Tenstorrent has been commissioned by the Japanese government, through NEDO*, to develop a training program for up to 200 Japanese silicon engineers to be brought up to speed on Tenstorrent’s designs. These 200 silicon engineers, over the course of five years, will come to the USA and work with Tenstorrent’s AI/ML technology. The first official cohort of engineers are being nominated now, from industry and leading universities as part of the NEDO program, and are projected to start in April 2025. The goal here is to train them on Tenstorrent’s IP and design stack, including the RISC-V Ascalon core and the AI Tensix cores, and that experience can be taken back to Japan to help cultivate strong engineers that know how to integrate high-performance IP.
On top of this, Tenstorrent is also expanding its Japanese operations. It already holds a localized sales office specifically for the Japanese market given the already sizeable interest in the technologies, however the company is also committing to developing a new CPU design team in the region.
What’s clear is that Tenstorrent wants to both be open but also meet their customers where their needs are. This new integration with Japan’s NEDO* and LSTC is a double-win for the company - the commission means they’re being paid to train engineers that will end up with specific expertise in Tenstorrent’s design flow, hardware, and software. That’s the sort of stuff that will propagate, leading to more extensive use of Tenstorrent designs in the region. Very few AI hardware startups can say something similar.
*NEDO: New Energy and Industrial Technology Development Organization
To date Tenstorrent has officially launched two generations of products - Greyskull and Wormhole, both 12 nm designs but stepping stones to expanding in both scale-up and scale-out when it comes to AI. Tenstorrent announced its Wormhole development kits and Galaxy enterprise solutions earlier this year.
The company is in progress to launch Blackhole, using its next-generation Tensix cores and built-in SiFive X280 RISC-V cores, within the next few quarters. The first in-house RISC-V core chiplet for lower power AI called Quasar, and the second for high-performance solutions called Aegis, are expected to come towards the end of 2025, both using Tenstorrent’s own Ascalon RISC-V cores.
We’ve interviewed several of Tenstorrent’s executives over the years, including CEO Jim Keller, Lead Architect Wei-Han Lien, CCO Keith Witek, and COO David Bennett. All of which shed light on different aspects of the business - I’m actually due an update from Jim at some point.
Also, all I need to do now is convince them it’s time for a media tour of their Japanese engagement. I’ve been covering the technology industry for almost 15 years at this point, and I’m still to get an invite to Japan. Hopefully with this reinvigoration of the semiconductor industry into the area, here’s my chance!
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