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PCI Express 7.0: Coming in 2027/2028
Initial Specification Now Live
It's easy to forget in the mélange of new standards coming into the industry specifically for artificial intelligence and machine learning hardware, enabling better memory support or compute expansion, that PCI Express (PCIe) is alive, well, and still growing in terms of adoption, addressable market, and feature set.
Today PCI-SIG, the standards group, is announcing at it's yearly DevCon that it will be making available the initial specification of the latest update: PCIe 7.0.
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For context here, I can say with a good deal of passion that the update from PCIe 3.0 to PCIe 4.0, which took seven years, was somewhat painful. There were some positives - having such a long lived standard kept a number of markets and designs stable. However near the end of the lifecycle, we saw increased demand for higher performance as a few key use cases for PCIe became more important - namely graphics, storage, and accelerated compute. Since that long drawn out step, PCI-SIG has committed to introducing updated standards for PCIe every three years, and to keep to that cadence with improved performance and features every year.
Every version of PCIe is designed to be backwards compatible, and PCIe 7.0 is no different. PCI-SIG is detailing a 2x transfer rate increase over PCIe 6.0, with the same PAM4 signaling and FLIT mode encoding. 128 gigatransfers per second is nothing to be sniffed at, which would enable 512 GB/sec operation in a full x16 configuration.
Version 0.3 of the specification is literally the base draft detailing the feature set goals but also the different permutations for lane counts and expected outputs. One PCIe lane of PCIe 7.0 is set for 32 GB/sec, which is the equivalent of sixteen lanes of PCIe 3.0:
PCI-SIG members, of which there are ~950 today, will all get access to the base draft in order to help prepare to develop new technologies and IP to achieve it. It will take a couple of years between today and the full release specification (v1.0), and then another couple of years for a test program to be put in place to ensure compliance. For perspective, the PCIe 5.0 standard was finished in March 2019, a compliance program in place April 2022, and we are seeing hardware supporting PCIe 5.0 in the market as of Q4 2022 followed by mass adoption through 2023. If we extrapolate this timeline, PCIe 7.0 should be introduced sometime in late 2027 or 2028.
Right now of course, PCI-SIG members are looking to PCIe 6.0, which had a full specification in January 2022, and a compliance program should be available early next year. PCIe 6.0 is actually a big change compared to PCIe 5.0, specifically the move to PAM4 signaling over NRZ (which means more bits per transfer), but also the encoding method changes into a FLIT mode, which we saw way back with Intel's (now Cornelis') Omni-Path technology. I find it interesting that in order to support backwards compatibility, PCIe 6.0 capable hardware will layer older encoding methods into FLITs to provide additional functionality.
A more recent big change for PCIe 5.0/6.0 standards is the introduction official cabling specifications. It has been clear that the latest and fastest versions of PCIe can be quite restrictive in terms of trace layouts, and customers are looking to break PCIe out both within a system as well as to the system next door, as well as backplanes. (I should also add, CXL requires a PCIe protocol base in order to work, so this benefits both.) A specifications release is targeted for Q4 this year to cover both internal cables (chip-to-chip, motherboard-to-accelerator, accelerator-to-backplane, motherboard-to-backplane) and external cables (board-to-board, rack-to-rack). PCIe 6.0 also features a low power feature (L0p), as a drive towards efficiency.
One of the reasons for this is the extensibility of PCIe. When speaking with PCI-SIG's President Al Yanes, he stated that there are many more use cases for PCIe today than ever before. For example in automotive, where efficiency might be lost using PCIe-to-X controllers and then back again, a direct PCIe connection/cable can reduce the amount of silicon required, increase security, decrease latency, and be easier to manage. Automotive is a key growth area for PCIe, according to the messaging.
<rant> Personally, my wish is that with new PCIe standards, certain hardware options (like M.2 SSDs), actually take advantage of the protocol by reducing the number of lanes in the product, therefore also saving energy and allowing for more expandability in a system.
For example, we now have PCIe 5.0 SSDs on the market, and all of them use four PCIe lanes. They could easily just use two, or even one, and still have the same performance as a PCIe 3.0 x4 retail SSD but with better controllers and better storage. Modern consumer platforms are looking at ways to improve expandability, but at the same time have to juggle how much PCIe IP is being used, how much is powered, and where savings can be made.
I'm all for new PCIe standards that push the boat in performance - it's very much needed. I just wish the industry took advantage of it for power and expandability, not just for performance. </rant>
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