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ElenaAnalysis's avatar

The roofline number stood out: an attention kernel going from under 1% to nearly 90% in about forty hours. If model-assisted kernel tuning holds up across workloads, the software moat around incumbent accelerators thins faster than most people model. Curious whether 216 GiB of HBM4 per part makes memory supply the binding constraint on scaling it.

Kai - Briefingblock's avatar

The fleet-level argument for one accelerator was the strongest part. Did Richard quantify how much utilization improves when prefill and decode ratios shift, compared with committing capacity to separate chips?

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