Companies Mentioned: $INTC, $TSM
Ahead of the April 25th Q1 financial results, today (April 2nd) Intel held a webinar related to an 8-K filing showcasing how the new business structure between Products and Foundry is going to be allocated on the balance sheet.
It was only a few weeks ago that Intel rebranded Foundry Services as Intel Foundry, and put the product-based business units (Client Computing Group CCG, Datacenter and AI DCAI, Network and Edge NEX) under a new branding of Intel Products. Intel was already showing Foundry as a separate business unit in recent filings, but the individual product teams still bore the cost of fab R&D for the process nodes they were expected to use.
In this update, Intel divides itself quite cleanly between Foundry, acting as a foundry, and Products, as if they were fab-less semi companies. That means all of the associated manufacturing, build-out, R&D, and ramp costs come under Foundry, no longer in Products. It’s quite a change.
In the 8-K, Intel retroactively applies this change to 2021, 2022, and 2023, breaking out the numbers using their best modelling techniques. Simply put, it looks like this:
This is a big shift in how we look at each business unit. All the product groups, which had operating margins anywhere from 0 to low single digits in previous quarters, are looking a lot healthier. In those previous disclosures, volume as well as ASP were talking points to drive margin and revenue. Under the new structure, a lot of that now falls under foundry, and it’s why Foundry has a negative operating margin. Gross margins are similarly low - zero, or negative if you include build out of new process nodes.
(It should also be noted that we see Altera here for the first time in the P&L as well).
This means that Intel has a long way to go to bring Foundry up to profitability. As part of the webinar and filing, Intel is talking about two major time frame references - its break-even point, and 2030. Intel is aligning this somewhat around what it’s calling a ‘pre-EUV’ and ‘post-EUV’ era, recognizing that cost per transistor for EUV based products is essentially half that of the non-EUV portfolio. On top of this, Intel believes its advanced packaging portfolio carries a good premium, and is divesting its traditional packaging business. At the break even point (for operating margin), Intel expects most of the margin to come from the EUV nodes:
This graph is a little confusing - while it’s meant to be about margin, the graph on the left specifically says wafer volume. It shows that Intel has a small wafer volume of EUV nodes today (only the Meteor Lake product which uses an Intel 4 tile is in production), however it will easily be double the pre-EUV product line at break-even. The margin breakdown suggests around 10 pts from transistor leadership, 18A. CEO Pat Gelsinger clarified that 18A is expecting to ramp in 2025, but will actually only hit the balance sheet in a meaningful way for margins in 2026. Realistically this would be in significant ramp to drive these margins and volumes, so break-even is very much a 2027-2028 statement. In fact, if I were looking at this graph as wafer volume, it suggests that Intel will be driving almost 2x the wafer volume at break even than it does today. Today, Intel creates around 2.5 million wafer starts per year, or ~200k a month. We could draw a line to the new fabs being built in Ohio, Germany, Israel, and the other USA sites to see where this volume would be built - however they still need customers to fill those fabs. Intel states it has a $15b order book (lifetime statement) currently, with more to come.
This is the 2030 statement.
We could easily overlay these graphs to predict where Intel thinks it will break even, and it is around the 2027-2028 timeframe. This means that Intel expects the back half of the decade, as it ramps 18A, 14A, and node variants, it will drive a lot of this margin and growth back to profitability. Pre-EUV still takes some of that volume, such as Intel 16 and the agreements with UMC for an Intel/UMC 12 node.
By far the most interesting graph of the call was this: a look at how Intel sees itself compared to the competition in Foundry.
This is only the Foundry nodes for external customers, hence why we have Intel 18A and not Intel 20A, but as we’ve covered before, you can in a lot of cases lump 20A and 18A in the same bucket. Same as with Intel 4 and Intel 3.
But based on social media comments, this graph is ‘kind-of hard to read’, so here’s the key:
- - is very behind
- is behind
= is roughly equal
+= is roughly equal or better
+ is better
++ is much better
While Intel doesn’t state TSMC as the competition, this is clearly a comparison against TSMC for the most part. This means:
Performance per watt: Intel is currently behind with Intel 7, will be roughly equal with Intel 3, match or outperform on 18A, and be comfortably ahead with 14A
Density: Intel is very behind on Intel 7, will remain behind on Intel 3, but will draw level with 18A, and then be equal or ahead with 14A
Wafer Cost: Intel is very behind on Intel 7 (It’s not an EUV process), remain behind with Intel 3, match pricing on 18A, and be ahead with 14A. Intel said in the webinar that it will be price competitive with where it should be in the market, but when it pulls ahead, will have a market leader pricing.
EDA: This is an interesting one, because Intel has been focused on its own EDA tools for decades. It now has relationships with all the major EDA vendors, and hopes to reach parity with the design tools by Intel 18A. It’s also another major reason why Intel’s focusing on 18A with external customers, rather than Intel 3.
Packaging: Intel says it’s ahead now, and will be even further ahead by 18A. This is fuelled by its plans in PowerVia, which right now the competition hasn’t talked about their comparative technology, and then Foveros (or a form of hybrid bonding). Personally I would think that external customers (Intel Gaudi included) trampling each other for TSMC CoWoS volume indicates that sometimes it’s about what you can produce in volume that matters most. But Intel is steadfast that its packaging technology is superior today regardless.
I think this is a nice graph, and shows us what Intel’s thinking at least.
One final slide, before the Analyst Q&A. Intel showed this one at their event in February, so not much new, but it’s important to think about where we’re going to be in 2030.
Highlights here are the 2000W TDP chips coming down the pipe, but also the Glass Substrate technology (which I’ve covered on my YouTube channel). In packaging, Intel is saying they have 9 micron hybrid bonding (Foveros Direct) in 2024, which will come down to 4 micron. TSMC has been shipping 9 micron for a number of years, so it will be interesting to see how that plays out. On the EMIB side, 8 HBMs today is the go-to for AI chips, however 12 HBMs will quickly become the standard, and beyond. There are companies, like Eliyan, working on technology to help double that by enabling longer range connections.
And with that, let’s head into the Analyst Q&A transcription. No paywall on this one, it was relatively short. Questions were transcribed live, so will have some minor inaccuracies, and will be provided as-is. Where possible, question asker will be shown. Answers were provided by CEO Pat Gelsinger or CTO David Zinsner.
Intel Financial Analyst Q&A
Q: Tim Arcuri, UBS: Can you bridge the new model vs prior standing model of 60/40, apples to apples, is it better/worse?
A: Our goal is 60/40 by 2030, same as before. We’ve been recutting the data, and while the trajectory slightly changes (a cycle hit for the drivers), but 60/40 has been on the cards. How we get there is now adjusted.
Q: Tim Arcuri, UBS: Operating Margin loading is back half of decade. Is this 18A/14A or 14A/10A ?
A: In 2025 we'll ramp Intel 3, and in 2026 we'll ramp 18A. 18A will be competitive in cost structure, competitive pricing, price/perf. Ramp of that into product really hits a large volume in 2027/2028. So it naturally rolls as we roll off Intel 10. 14A makes it better, but that doesn't qualify into 2027, hits P&L in 2028. It cascades because Semi has ramp timing, being a portion of the business model. The effects of mature nodes tapers down, and we’re on track to deliver the pre-EUV and post-EUV era for Intel. We're competitive, and coming back to leadership. Post-EUV will be enabled by very few companies - that offers a scarcity value for those nodes. The bulk of our wafers will be Intel, but at the back-end of the decade, we’ll get external wafers. They start to offset smart capital, and show our competitiveness.
A: When we get to break even, we're half-way there in gross margin, but the effects will show up meaningfully by mid-point. We see more to drive 40% Op Margin. 2024/2025 are slower, 2024 is a trough on foundry in operating margin expansion, mostly due to fab and node startup costs. Once we get out, it'll show in P&L.
Q: Joe Moore, Morgan Stanley: Where you allocated costs on process tech on process development, is that IFS, or shared? Are these now two separate orgs?
A: We're treating Foundry like a foundry. It carries capacity cost, depreciation cost, R&D tech, and it sells wafers competitive to industry. Intel Products will now act like a fabless semi based on the pricing and the established industry costs. We benchmarked against the market to bring this model. Products group now look at all of these pricing and costs, compared to before where they didn’t need to. Foundry will build the technology and the roadmap to meet the internal and external foundry requirements. Building the clean legal separation, rebuilding the ERP, and the data flows so external customers can have confidential info segmented from the rest of our business. We have Foundry with separate fab-less Products business.
Q: Joe Moore, Morgan Stanley: Book value would grow to IFS side?
A: As the biggest part of our PP&E, most of that will go on foundry. Within a couple years, that's a $100b number. For valuation, even the worst foundries get 2x value, others get a lot more. That's where value will come, and generate return.
A: Sustained profitability on products on a proper market basis as you look at the parts value for Intel over time.
Q: Vivek Aria, BoA: Starting GM for Product and Foundry to compare to longer time? What are the Free Cash Flow targets?
A: That's part of the 8-K. Rough order, +/- 50% GM business on products, and foundry is negative GM. Slide showed wafer margins at 0% at Intel 7 pre-EUV - once you add start-up costs, that's a negative margin. This means there are lots of opportunities.
Q: Vivek Aria, BoA: At analyst day, you had targets for 2026. Now you have targets to 2030. What are the differences in the market since those numbers?
A: If we build up from process technology, our 5N4Y (five nodes in four years), the costs of that, the pathway to profit - there is no change. We aim to be product competitive, and we're on track. There have been a couple of major changes we weren't expecting: the market cycles post-COVID. Stronger PC growth was expected in that timeframe, and we wanted more success in accelerators. What we've laid out today are reasonable modest assumptions - mid-to-low single digits gains, for AI accelerators over time, growth in foundry business in cycle, leading to mid-upper single digits. We see lots of opportunity to beat those, as we built this model: the scarcity value of being an EUV foundry, the deal value, the important competitiveness and new categories like AIPC will drive growth. We believe the segment will drive the right business characteristics internally. We’ve segmented Altera and Mobileye - today's model is well underway. The Foundry revenue is great opportunity for growth.
Q: Aaron Rakers, Wells Fargo: Product operating margin (OM) trajectory. If I’m looking at the recast of DCAI/CCG, that was 13% OM in 2023. What's the right normalization proiule in that business? in 2021 it was 44% or so.
A: 44% is the sort of OM you should see in that business with a good margin profile. That's the goal for sure. We’re investing in accelerators, in businesses that have negligible revenue today. That means good operating expenditure (OpEx) leverage. Lots of what we're spending in OpEx is where we can sustain it. We have the opportunity for efficiency as businesses grow.
A: In DCAI, this is first area we'll see Intel 3. Granite Rapids (GNR) and Sierra Forest (SRF) coming to market. We're going to have process technology leadership there for the first time in a while. Intel 3 from foundry has better margins too. It will be the first moment we see Foundry and Products ramping together. Those will hit P&L significantly next year, but we also have Clearwater Forest (CWF) coming with 18A - even better cost from foundry, and better competitiveness. We’re starting to bring accelerators to the marketplace - Gaudi, Falcon Shores. Bring business back to profitability we expect.
Q: Aaron Rakers, Wells Fargo: On IFS, now we unpack - as you change the cadence from 5N4Y back to 2N1Y (tick-tock), how do you depreciate equipment in IFS? Or is this an opportunity to extend life of that equipment?
A: In reality, we already moved depreciation of equipment to 8 years anyway. We don't expect that to change, but we will evaluate. We will get better use of the assets, which has better return on investor capital.
A: We put lot of emphasis on life extension of equipment. It’s important for our business model. When we get over EUV, we have the most modern productive EUV fleet in the industry. We have a good reuse between equipment. We're also doing more node variations. Advanced packaging will also extend life, as well as relationships with UMC. All become rich portions of improving ROIC. The cost per transistor for post-EUV is half of pre-EUV. This means it’s cost effective to go to EUV, and we're leveraging smart capital and the AI era to drive significant value in the business model.
Q: Vijay Rikesh, Mizuho Securities: The foundry revenue to 2027/2030 - what are the revenue expectations as you drive margins?
A: Today it's small - but it ramps smoothly. We expect >$15B revenue by the end of the period. We also expect more than double that from internal. We are going for #2 foundry based on external revenue.
A: On margins, we expect a model margin of 40%. We see that on wafers and advanced packaging. They are rich margins on a relative basis. From a wafer margin perspective, packaging should actually be higher. But startup costs will lock in that 40%.
A: The better cost structures will bring wafer pricing in and bring share. Leadership will command leadership pricing too.
Q: Vijay Rikesh, Mizuho Securities: Intel Products - mix of insourcing and outsourcing foundry in that margin out to 2030?
A: We expect to bring some wafers home. We're peaking external use today, but we expect the smart capital to use external over time but at a lesser scale. Those foundry relationships are super important, but will be less critical for P&L. Peaking in 2024/2025, but moderating over time. We use external for some specific nodes we don't have, for capacity balance, or just because they've got features we don't have. These are important relationships for Intel. It's built into the model.
Q: Sri Pajuri (Couldn’t hear) What % of revenue is outsourced today? What extent is foundry break-even based on insourcing?
A: 30% of wafers today are from external foundry. We'll be insourcing a couple of fab modules, and will pivot that number down to 20% over the period. It helps us in cost, consolidation, and also extend the life of our nodes. Also supply demands, supply control is a benefit.
A: We have a good line of sight for Intel products to bring back. We've modeled conservatively.
Q: Did you say 2026 for 18A volume, 2025 for 3 volume?
A: 18A goes into volume in 2025, however the volume and impact P&L will be 2026. The bulk of wafers in 2025 are Intel 3. Good amounts of Intel 3 in 2025. 18A wafers in 2026. No change in schedule. Ramping Panther Lake, CWF. Everything is looking good!
Q: CJ Muse, Cantor Fitzgerald: Products and Foundry - how early does Products need to commit to Foundry?
A: It's not atypical from any foundry that would be chosen. In this case, the critical aspects, our internal customer teams are driven to be customer zero and drive the deep collaboration in EDA, IP. It's what makes it a great model. We're driving those designs, so it might appear that Products has to engage earlier compared to other foundry. The bulk of wafers are in the life for external - we're pricing our wafers with competitive technology at below market prices to drive revenues and volumes. This is a capacity corridor between Intel Product and Foundry. We are building new muscles of how Intel works as a foundry and as a fab-less product business. We are rebuilding ERP, IP management, all now well underway. Proud of progress.
Q: CJ Muse, Cantor Fitzgerald: Your numbers state $19b in Foundry revenue in 2023. To get to break even, what revenues are you thinking about - what's internal/external?
A: At a high level, we don't need revenue growth. The underlying improvement of 18A, the margins of 18A, the move of our tiles, and the efficiencies are starting to see. All of those things are not a function of volume. We get to break even with modest growth. We have $15b of external foundry deal value. We're going to get growth, but we don't really need it.
A: 66-70% of wafers internal, 30% external at that point in time. My objective is to grow external business as fast as I can, to drive next generation leading products on Intel foundry. We need to give customers confidence to trust Intel, in order to drive their business through Intel foundry. They have expectations on foundry, and we have to offer them. The assumptions are reasonable. The energy out of our events are very profound - the EDA, the IP. We have had Testimonials from Arm, Rene Haas - 18A, world class PPA. Full cadre of IP support. All these pieces are coming together. We want to be the foundry of choice in this AI era. It begins with packaging, and building momentum with the industry.
Based upon how MTL and EMR performs vs their AMD counterparts and what Intel has publicly stated wrt perf per watt for 5N4Y, it seems like in that slide Intel is comparing Intel3 to TSMC N3E and 18A to N2, do you agree, Ian?