Note: This is a written version of a video posted to my YouTube channel.

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There's a battle in the world that happening at the microscopic scale. In this newsletter we talk about the products that come from sand, from silicon, that we fired electric bolts at and we've taught it to think. As dangerous as this might seem, people are looking at better ways to build that silicon in order to get the highest performance, the highest efficiency, and the densest design. We're talking the world of transistors, and would you believe that the industry is actually aligning on a few things coming up in the future. Some even have roadmaps going out to 2036.

So to put things into perspective, when we're talking about manufacturing the leading edge silicon technology, there are three companies we typically talk about: Samsung, TSMC, and Intel. These are the only three that claim to be producing leading edge silicon in volume (whether or not you agree with that is a different matter), and these companies rely on a wide range of partners in order to even get to that state. The most common partner I often mention is ASML, as they are the only company in the world that builds and sells EUVL (extreme ultra violet lithography) machines to make these miniaturized features. But alongside ASML who focuses solely on patterning (and has its own suppliers), there are dozens of other companies involved in the industry pushing the boundaries - Tokyo Electron, Applied Materials, LAM Research, and others that actually build the tools to make the chips. Then beyond that, there are companies involved in packaging, dicing, and then the materials research that goes into it all.

Materials Research is a key phrase here, and generally covers the underlying design and structures built with the processes. The research itself comes from a number of sources - every big foundry has their own team, there are even fabless semiconductor companies working on specifics, but there are also a lot of academic institutions involved in doing the research. Between commercial and academic, there are a number of partnerships at play, as you’ll often see academic research papers acknowledge Intel or TSMC or Samsung. On the wider scope, we have larger institutions dong the research, and one of those is called imec.

Based in Belgium, imec is one of the leading research conglomerates looking at new materials and new functionality for next generation semiconductors. If there's one thing Europe does well in semiconductors, it's the research. A few weeks ago, imec held a Technology Forum at the Design Automation Conference in San Francisco, and I just happened to be in town. It was a few hours of talks over an afternoon, going into the direction of the research and some of the business details.

But what I really want to cover is what I mentioned in my intro - how do we get better transistors? Thankfully, imec provided a roadmap going all the way out to 2036, covering a number of needed innovations - most of which I've been seeing pop up recently at research conferences. Then there’s also the naming of all of these process nodes.

I'm going to go through this slide in stages, so we can talk about each part.

We should talk about a couple of these terms, especially if you've never heard of them before.

When you build chips, you build them out of what are called libraries, and cells, underneath of which are the transistors. In a transistor, the distance between two transistor gates is the metal pitch. But normally we don't speak in design about individual transistors, but about transistor cells as our base unit. A cell is made up of multiple metal tracks. It's the number of metal tracks multiplied by the metal pitch that gives the height of the cell.

So when we talk about density, the number of transistors per unit area, typically we're not talking about shrinking the transistor itself, but the cell area. If you can reduce either the metal pitch, or the number of metal tracks, then this increases the transistor density.

So lower numbers are good. Smaller numbers = more dense transistors.

From History to Today

So going through this roadmap, the first stake of this roadmap covers 2018, where the leading edge process node was N7. We had 40 nm metal pitches, 7 track FinFET libraries are the mainstay of the market.

Moving to 2020, we have 5nm or N5, which is a 6 track FinFET library, and 28 nanometer metal pitch. Moving from 40 to 28 is a sizeable jump, but the market is there already, and companies like TSMC are showcasing reduced track libraries for a large swathe of the fixed function silicon market.

For 2022, so this year, we're talking N3 / 3nm. This process node is what Samsung says they have started to produce, and TSMC is saying it will be manufacturing ready by the end of the year. In imec’s roadmap, this is still a 6-track FinFET library, but 22nm metal pitch. There are a lot of designs in the industry talking about N3 given that it is the last generation of TSMC FinFETs.

The Future

The first future generation, as you may already know if you follow this, is in 2024 and 2nm/N2. This is the first Gate-All-Around technology, also known as nanosheets or nanoribbons or MCBFETs – the marketing teams at each of the major foundries are wanting to call it something different in order to differentiate. Metal Pitch and metal tracks don't change much here, as the focus is on getting the new technology to work. GAA designs are expected to allow chip designers to be a lot more flexible in how they design silicon IP: FinFETs have a cell drive current limited by the discrete number of gate fins in use, whereas GAA uses the equivalent of a variable width gate sheet, making it a more continuous selection. Instead of selecting 3, 4, 5,or 6 fins, a designer can use anywhere from 12 nanometer sheets to 40 nanometer sheets and any number in-between, depending on the desired characteristics of performance and density.

In 2026, this is where imec will change its nomenclature for process nodes. The node name is meant to represent the equivalent planar transistor pitch, not an actual size, so as we go below that 2nm theoretical planar transistor, the companies are going to talk about Angstroms. A nanometer is a billionth of a meter, whereas an angstrom is a 10 billionth of a meter – this means 10 angstroms make a nanometer. In 2024 we spoke about 2nm, which would be 20A. Intel is calling it 20A for example, whereas TSMC sticks to 2nm.

In 2026, imec is saying it will be the A14 node. Node that there is no 18A here, that seems to be an Intel thing. A14 / 14A (again, as these are names, it really doesn’t matter where the A is), the main jump in the material research is going from a 6 metal track design to a five metal track design to increase density.

Now in 2028, instead of going with gate-all-around transistors, imec is saying the industry will move to a variation of gate-all-around, known as forksheets. The research on forksheet today is well underway, but it is important to note that it's a denser version of gate-all-around. imec calls this the A10 process. In a forksheet, rather than the NMOS and PMOS transistors being physically separated with a gap, they are now separated with a barrier, which is smaller width than what the gap used to be. It also means that in order to make the sheets, the etching profile is changed, which may make things harder or easier depending on the method.

In 2030 we get the fourth generation of GAA, the second generation of forksheet, and this seems to be mostly optimizations for A7. That 16nm metal pitch is a super small metal pitch.

Divergence

From here, I should note that roadmaps differ whether you're speaking to imec, TSMC, Intel, Samsung, etc. There are a lot of variations past this point. I'll start with imec's listing, as that’s the one we have.

In 2032, we move away from forksheets to what the industry is calling CFETs. A Complimentary FET (CFET) looks like a stacked gate-all-around transistor, because it is. Now we are stacking PMOS on NMOS (or the other way around), which should theoretically double the density from standard 1st/2nd generation gate-all-around designs.

It sounds like a win for density, but one of the key barriers to CFETs is thermal stress during manufacturing - in order to make some of these nanosheets, high temperatures are used in the early stages. If high temperatures are used for the stacked design, you might end up warping what you’ve already made, and damage the design. When it comes to building the sheets on top of the CFET, these have to be done with lower temperature methods in order to keep everything the way it should be. So far I've seen Intel speak about very basic CFET design in research, so it's clearly being looked at. This CFET is the A5 node on imec's list, and also that density increase comes with metal track reduction - when you go vertical, there may be additional cell benefits as well, or more issues to solve.

In 2034, imec doesn't detail much change in the A3 node, but we are talking 12 years away at this point.

Lastly, In 2036, this is where imec says it expects atomic level sheets to be used in the designs. By atomic sheets, what we really talk about here is 2D transistors. For anyone following the research, this means materials like MoS2 (Molybdenum Disulphide) or WS2 (Tungsten Disulphide) that form self-assembly 2D structures and can be used as transistor materials.

For everyone asking if we're ever going to move beyond silicon as a material for making transistors, then this is the point where it gets real for the gate material itself. There is already a lot of research going on when it comes to 2D transistors, mostly in terms of simply growing and profiling the damn stuff. If I recall, there was a paper at ISSCC or IEDM that managed to grow a 4-inch monolayer (i.e. 1 layer) on silicon. One of the main problems with 2D materials is that they like to form up to 5 layers or more, so if you only want one layer, it can be a bit of a pain, and it needs to be controlled.

Everyone Else

So in terms of other roadmaps I've seen, TSMC has shared one that I can't share with you, but while it doesn't mention forksheets, it does talk about CFETs and 2D transistors. It separates it into two phases – pre-2028 is GAA and CFET, and beyond 2028 is 2D but a lot more vague and, as I was told, ‘aspirational based on research’.

IBM, who partners with a few of these players, has been working on VTFET technology, or vertical transistors - basically taking the concept of a transistor and making it work at 90-degrees. The idea here is that it might be denser and/or easier to manufacture, however I've not seen it on any of the main player roadmaps yet. IBM did speak about it earlier this year or late last year, but as they were the only one I didn't pay much attention to it at the time.

Samsung’s roadmap is also akin to a TSMC like future, except it is enabling GAA earlier on 3nm, and beyond 2025 hasn’t really been presented in a public forum.

On the role of 2D transistors, there was that Nature paper last year that people seem to think implied '1nm transistors' that came out of TSMC in collaboration with others, however as I have kept saying since that paper came out, that is a gross misreading of one of the graphs that merely extrapolates a line down to 1 nanometer. The paper was actually more concerned about how to connect 2D materials like MoS2 to the rest of the chip by using non-contacting bismuth and relying on electron band-gap manipulation. It's a fascinating paper that I think was taken so far outside of what it was talking about, the real magic inside the research was lost. Oh well, that's mainstream media who just read a simplified story for you, rather than actually reading the research and understanding it..

More Than Just Transistors

So one thing not addressed in this simple roadmap slide is a lot of what else goes into building a chip. We're seeing a variety of players (Intel, Arm) talk about features like backside power delivery (what Intel calls PowerVIA) becoming more important, and then there's packaging - companies like Graphcore using wafer-on-wafer bonding for their deep trench capacitors providing 30% extra frequency by moving certain elements outside the main core design seems to help a lot. Then there's the question of EUV, patterning, High-NA EUV, and what the post-EUV ecosystem might look like.

I'll end this by giving you a quick reminder: EUV was being talked about in the 1980s. Back then it was called Soft X-Rays. In those days, based on technology development, it was widely accepted that EUV would come to market around the same time as 180 nanometer process node, or the early 2000s. It took until the late 2010s for the technology to be realised, and in 2022, we're now in high-volume EUV. The power efficiency of creating chips with EUV is crazy low - 10s or 100s of kilowatt power sources enable a 500 W laser to shoot tin droplets which provide 40 mJ per square millimeter of silicon. One of the main issues with EUV has been power, along with picometer-accuracy level mirrors, and masks, and photo-resists. While there discussions about what might be beyond EUV, beyond 13.5nm wavelength silicon design, the effort to get there is likely going to require an order of magnitude more innovation.

I'm not sure if there'll be a new source beyond 13.5nm EUV in my lifetime. I’ll be quite happy to be proved wrong however.

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More Than Moore

imec's Roadmap to 2D Transistors in 2036