As we toured the tool, about 15 of us or so with CNBC wielding a pre-approved camera setup, the question was if/when this tool was ever going to be involved in production silicon and hardware.

The answer landed on July 15, 2026. ASML put out a press release confirming that Intel Foundry has taken High-NA into high-volume manufacturing. Using the tool, Intel is patterning a subset of layers on some of its newest notebook processors: these are Panther Lake, the Core Ultra Series 3 laptop parts built on Intel 18A.

From Intel and ASML’s point of view, it means those High-NA layers are dual-qualified in Oregon, and yielding on par with the regular EUV tools that require multiple steps to do the same thing. I asked if this was just test chips, but Intel confirmed it means that notebooks with silicon partly printed on a $380 million High-NA scanner are heading to customers now.

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Intel has been able to say it owns the world’s first High-NA tool since that 2024 tour, but there has always been a question of using tools like this for research time over production time. Getting product layers through the machine at a yield that matches the mature scanner one bay over is a big step to overcome, the next question is if the economics of a single pass on a more expensive machine work out long term.

What the machine actually is

The machine is a two-storey wall of stainless pipework, vacuum vessels and cabling wrapped around a wafer stage, and almost all of it is to serve one number in physics. Every EUV scanner in production until now has imaged through optics with a Numerical Aperture (NA) of 0.33. Numerical aperture describes how wide a cone of light the optics can gather, and a wider cone resolves finer detail, so raising it to 0.55 with High-NA sharpens the smallest single-exposure feature by roughly a third. In practice that lets a fab print in a single cycle a pattern that would need two or three aligned Low-NA exposures stitched together. Each exposure removed takes its cost, its cycle time, and one of its defect opportunities with it - in short, fewer exposures are usually better.

Reaching 0.55 was not free, not only with the machine cost but with physics and chip production as well. ASML moved to camera-style anamorphic optics that magnify the mask by different amounts along the two axes - in literal terms this halves the field that the scanner can image in a single shot. Instead of an 858 mm² chip, or 26 x 33 millimetres, the maximum an EUV machine can do is 429 mm², or 26 by 16.5 millimeters.

A full-reticle die now has to be exposed in two halves and stitched back together, which complicates some of the process simplicity the higher resolution was meant to provide.

A single system costs close to $380 million, roughly 2-3 times a Low-NA scanner, and installing one runs to around 250 crates and several months of work on site. Those two facts, a high per-tool cost and a per-exposure penalty set against fewer process steps, have called into question its pricing efficacy.

Where High-NA belongs on the roadmap

Where High-NA will do its real work is longer term - as shown by imec’s long term roadmap. On that timeline, 0.33 NA EUV carries the metal-pitch scaling from the N7 era down to about N2, taking pitch from roughly 40 nm to around 21. Compare that to High-NA 0.55 EUV, we extend down to A14 and through to A5 or so. In roadmap terms High-NA is a decade-long tool whose job begins in earnest soon but will carry through into the 2030s.

So why is Intel running it on 18A (its N2 equivalent)? 18A was designed around Low-NA EUV and multi-patterning, and the hardware Intel designed for it does not depend on High-NA to ship. Part of the difficulty of any new technology is ensuring it at least matches what it is replacing, and that’s why the layers on Panther Lake are dual-qualified on both Low-NA and High-NA, rather than just High-NA required. Intel has threaded the machine into a node that would be fine without it, so that by the time 14A/10A arrives and High-NA becomes more of a necessity, its people and its process recipes have done their learning already. If an 18A wafer went wrong, it’s not a big deal for the products until it gets dialed in - and Intel is now saying it’s dialed in.

People who follow Intel will understand that this is the reverse of the last transition, when Intel dragged its feet on EUV in the 10nm era and paid for the caution with years of delay. This time it is the one out front, and TSMC is the one waiting.

The cost argument that Intel ignored

The fair question is whether any of this is worth the money, and the skeptical answer comes from SemiAnalysis. Coming from IBM’s work on High-NA at a 2025 conference, they explain that a single High-NA exposure costs about two and a half times a Low-NA one. At that ratio, the new tool only pays when that one shot replaces enough cheaper ones. SemiAnalysis’ modeling put the crossover for most layers somewhere around 2030, with Low-NA double-patterning cheaper until a pattern needs three masks or more.

From a physics perspective, another factor is dose. To get the smallest layers, you need more EUV power, aka a higher dose, but a higher dose forces the scanner to dwell longer on each field. A slower scanner prints fewer wafers an hour, which pushes cost per wafer back up. TSMC has read the same math conservatively, skipping High-NA for its 2nm and A16 nodes and still being relatively non-committal through 2029, despite purchasing machines for testing.

What the bear case tends to underweight is that none of this has kept the machine from selling. ASML had ten to twenty High-NA orders booked by early 2024, and not only from Intel: SK hynix ordered too, and became the first memory maker to install a commercial system in late 2025. Samsung is also working with the tool(s) they’ve ordered. Even NY state has ordered one, being installed in Albany - to be primarily leased to IBM. ASML is building something like twelve to fifteen systems a year now and has guided to roughly twenty a year by 2028.

The objection regarding throughput and wafers per hour is being solved as well. The tool I saw back in 2024 was an EXE:5000 model, built for R&D volumes. The production EXE:5200B that Intel accepted at D1X in late 2025 runs about 175 wafers an hour at 0.7 nm overlay, a lift of roughly 60 percent, and ASML’s larger 6-by-12-inch mask is meant to cut the stitching overhead the halved field imposes. IBM in their paper also put up SPIE overlay data they argued showed no meaningful penalty from stitching.

The two sides are not really disputing arithmetic. Many analysts are trying to count the dollars per exposure. The foundries using the tool are also counting the exposures, masks, alignment steps, and defects they no longer have by only running once, not multi-patterning. Panther Lake is the first shipping evidence in that argument, and a matched-yield result is a strong point for the side that says the tool is ready to work.

Will I Ever Know?

No. I asked if Intel plans to SKU the High-NA parts differently so you could rock up at the office with a High-NA chip to gloat, but alas it looks like the hardware will just be run-of-the-mill parts bundled into the rest of them. I’m sure Intel will still be tracking by batch the long-term effects just in case, but the public will just get a CPU.

With Intel’s financials for the quarter quickly approaching, I can imagine some of the analysts on the call will be asking for volumes so far. I suspect it will fluctuate based on R&D uses for these tools, then when idle just pump a few Panther Lake wafers through to amortize some of the cost. In my first trip to D1X, I remember seeing a row of five Low-NA EUV machines all up and running, with at least a dozen more set for the facility as a whole. That’s how a foundry gets volume, so keeping track of Intel’s High-NA orders might be a good indicator for how confident they are long term about yield, quality, and cost.

Intel have already said that for external customers on 14A, High-NA will be an option - take it and you’ll have a faster time to market due to fewer steps, likely at an additional cost for next-day or two-day shipping.

Sources

• https://www.asml.com/en/news/press-releases/2026/high-na-euv-reaches-new-readiness-milestone

• https://newsroom.intel.com/press-kit/intel-high-na-euv

• https://research.ibm.com/publications/accelerating-high-na-euv-lithography-insertion-for-interconnect-scaling-and-beyond-performance-cost-and-future-prospects

• https://research.ibm.com/publications/multi-reticle-stitching-applications-from-packaging-to-high-na-euv

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More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, AlphaSights, Applied Materials, Arm, Armari, Arteris, ASM, Ayar Labs, Baidu, Bolt Graphics, Cadence, Credo, d-Matrix, Dialectica, Facebook, GigaIO, GIM, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, Marvell, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Rebellions, SiFive, SIG, SiTime, Supermicro, Synopsys, Tensordyne, Tenstorrent, Third Bridge, TSMC, Tsavorite, Untether AI, Ventana Micro.

The shift has changed the economics of memory in a very visible way. The industry has spent decades thinking in cycles, with familiar waves of overcapacity and correction, but the current environment feels different. AI has pushed memory further up the value stack, turning it from something many treated as a commodity into one of the key battlegrounds in the buildout of next-generation infrastructure. The biggest companies in the world are now competing not just for compute, but for access to the fastest and densest memory subsystems, and for the storage needed to make those systems useful at scale. As pointed out in this interview, what we are seeing now is not demand appearing from nowhere, but years of expanding use cases across servers, smartphones, automotive, and cloud - finally being supercharged by AI.

Joining me for this discussion is Praveen Vaidyanathan, VP and GM of Cloud Memory Products in Micron’s Cloud Memory Business Unit. His remit covers the memory technologies now sitting at the heart of modern data center design, from HBM and LPDDR based server solutions through to the storage products increasingly used alongside accelerated compute. In this conversation, we talk about whether this really is just another memory cycle, what changed as AI demand accelerated, how Micron is thinking about HBM4, custom memory, SOCAMM, LPDDR6, and PCIe Gen 6 SSDs, and what it means to plan capacity years in advance in a market where demand can suddenly look very different in the space of a single quarter.

The following is a tidied up transcription of the interview.

Ian Cutress: So the first question is: is this a cycle? This is the memory industry, We’re so used to ups and downs. What makes this one different?

Praveen Vaidyanathan: I think whether it’s a cycle or not - if you look at history, [then] yes. However, whether something is a cycle or not, we will know three years from now. Do I really know today? Probably not. But I think what is happening with the current scenario is really the underlying fundamentals that are driving this cycle in terms of the demand drivers. Where do people need memory? If I look at going back to the 80s and 90s where people used to think of memory as a PC component, that’s where it all started.

It was a KB number; now it’s a very different number these days. That’s where it started, but it then progressed into every single application. You talked about consumer; the advent of the smartphone changed what consumer looks like. So that provided another outlet and then it walked into automotive. Automotive applications today require memory, and then servers came along. So the presence of memory across the entire user space has proliferated so much and I think this has been building over time. And now the super cycle is that history that has built up, and now AI has come upon and that has catapulted and surged the demand for memory and application. So I think it’s fundamental to how systems are architected today and we are looking forward to working in this environment.

Ian Cutress: You say it’s built up over time, but if I look at recent history, the last six months, I think Q4 in ‘25 people suddenly went, “Wait, what? It’s not a commodity anymore”. What changed that quarter?

Praveen Vaidyanathan: We think there are maybe a couple of things going on. I think as AI came on - let’s say 2022 time frame, when the whiff of generative AI happened with ChatGPT - and people started using that more, there was a lot of investment in core AI infrastructure which was very much accelerated compute. And as people invested in that, I think there were two things that happened: the continuous growth in frontier models and the cost of tokens coming down has increased the usage of AI applications.

Ian Cutress: Jevon’s paradox sort of thing - make it cheaper and people will use it.

Praveen Vaidyanathan: Exactly. I think that is happening, and could you predict this? Not when models are evolving on a three-month cycle time. You don’t really predict this. So that has resulted in a surge in demand. Along with accelerator compute, I think there is also a lot of supporting compute around it that people did not invest in long enough and suddenly that investment became necessary. So the two put together kind of came together at the same time. But in this industry, I don’t know why we should be surprised about things happening suddenly. How many times has that happened? And then we all look back and say, “Of course, it’s obvious,”.

Ian Cutress: This is why companies like Micron and your competitors are investing every generation in new technology. We track where the tools are being sold for the latest generation process nodes and the topic of the day right now is this transition from HBM3 to HBM4, and we’re seeing a different number of constraints around HBM4. Can you explain how they look at Micron?

Praveen Vaidyanathan: So we actually just announced at GTC that we are in volume production with our HBM4. We hit volume production with HBM3E last year and now we are here with the HBM4. HBM4 does two things. One is it allows you to improve the bandwidth of the memory attached to your GPU. The second is it continues to improve the power efficiency curve because you want more bandwidth, you want more performance, but you are limited by the power envelope. So it does that, but every generation of HBM also has more manufacturing complexities. It takes longer cycle times to produce. So you have to innovate not just on the product cycle and product capabilities; you have to innovate on the manufacturing also. As soon as you have this product, everybody wants it and they want to go push the product in the market. So innovating on the manufacturing cycle times and manufacturing efficiency is another thing that we have to keep working on.

Ian Cutress: One of the things that always strikes me is that HBM and the JEDEC standards almost seem to be misaligned a little bit, as in JEDEC might be a bit too slow and the demand for HBM might be a little fast. That’s where we’re getting situations where you’ve got a big partner like Nvidia asking for faster than JEDEC. So what extra has to go in to essentially provide that product line for such a big customer?

Praveen Vaidyanathan: I think it’s true for them and a few other customers also. I think what you have to understand is it always starts with “what do the customers want?”. So we talk to them ahead of time to try to figure out what they want. But we do also have to think a little bit ahead and think about what does the industry need. If bandwidth is the key capability of HBM, then that’s what you’ve got to shoot past the puck a little bit to be ready with something.

JEDEC is interesting - it doesn’t limit what you can do. It just provides a common platform. It makes it a commodity, but you can still innovate. For example, HBM4 still meets all JEDEC requirements, but it’s faster. Because we all said, “We’re going to design faster”. Our customers said “we want to go there”, so we went there. So, we do think about how we operate within both environments because honestly, having a standardization helps adoption. Everybody can take it and use it, so that helps. But also, the commodity piece of it is not great, which is why custom HBM has come on, where some people want a little bit more than that and they are willing to work with us on that.

Ian Cutress: In terms of custom, JEDEC defines a specific size of HBM and how many stacks you can go up to based on bonding and other specifications. Are you seeing customers who want different XY dimensions or different heights, beyond standard stuff like that?

Praveen Vaidyanathan: It could go there, who knows. But that’s not where the current trend is. The current trend is you want to keep a few things constant, but within that, what more can you do? We think it’s going to be more functions and features that you can incorporate that are not part of your standard JEDEC offering.

This is why we have the logic base dies. That allows you to do more with it once you go to an advanced logic-based die you can do more with it.

Ian Cutress: You seem to be doing something a little different on your base die because you’re using an internal 20nm process rather than a TSMC N3 or Samsung Foundry SF4. What benefits does that bring you?

Praveen Vaidyanathan: I think that’s a great question, Ian. I don’t think we’ve said 20, it’s just a general internal logic process for us, but it starts off from the very beginning from a design methodology perspective. When we did our HBM3E, we kind of anticipated that as you scale this technology, innovating on the DRAM stack is going to be most important because that’s what - as you go from 8-Hi to 12-Hi to 16-Hi - you have one base die, but you have lots of DRAM on there. So if you want to think about performance and power optimization, innovate on the DRAM, get to the best DRAM you can, and then bolt on the best logic die that you can get.

Our HBM3E was actually 30% more power efficient than any other HBM3E out there. So we had a little bit of an advantage over that. And if you go to HBM4, the same advantage: we were able to get another 20% improvement before HBM3E, so we had less to gain from going to an advanced logic node on the base die and we had all our innovations on the top die. We evaluated everything. We said, “Hey, we want to be paranoid that we’re missing something,”.

I think we all grew up as engineers. It’s hard to get away from that. That mindset really helps: have the paranoia, go evaluate everything. We came back to the conclusion that we’ll be able to meet the speeds and performance that the market requires with our own logic. And this also reduces our risk because now we are all in-house. We don’t have to have an external dependence. We have a mature DRAM technology that is the same between HBM3E and HBM4. So less change, less risk, and faster ability to ramp. That was the decision that we made over a very long life cycle in probably three minutes, but those were the key tenets of that.

Ian Cutress: How integrated are you with the packaging firms? Because a lot of this HBM is in a CoWoS or a cube type formation. I assume you’ve got to make sure it’s all compatible with them.

Praveen Vaidyanathan: Absolutely. We have a packaging team that is working ahead of time; in fact, a significant portion of our packaging team is stationed in Taiwan, which is where all the action is. So we work very closely with both our internal manufacturing teams and our external manufacturing partners to deliver these things. It’s a co-design; packaging design starts at the same time as silicon design. They have to be fully integrated. Some of the things I talked about, like the power advantage we had, we actually had some packaging techniques incorporated in there that help with lower power consumption.

Ian Cutress: Like integrated deep trench capacitors and that sort of thing?

Praveen Vaidyanathan: We don’t do integrated deep trench capacitors, but it’s more about TSVs and pitches and how many metal pillars you have to conduct heat. You help design with packaging and the two come together. It gets more complex over time.

Ian Cutress: At GTC, Nvidia mentioned HBM3, HBM3E, HBM4, HBM4E, then HBM custom. I’ve already got people asking me: is that truly custom or is it still standards-based to a certain degree?

Praveen Vaidyanathan: I can’t speak for Nvidia of course, but we have publicly stated that we expect a parallel product line. There will always be a generic product line, but we will also have a custom product line for certain customers who are able to extract additional value. So I don’t think it’s an either-or answer; there are certain use cases that work really well with JEDEC and there are certain use cases that will require the custom HBM.

Ian Cutress: Because demand is so high, how do memory companies like yourself decide when to increase manufacturing capacity? These things don’t spin up overnight; it requires 20+ billion dollars and 3 or 4 years of effort. If you can predict then you can build, but if you can’t predict it becomes difficult.

Praveen Vaidyanathan: Broadly it’s part of our planning cycles. Let me give you some examples that illustrate the results of our planning. If you look at some of the announcements we’ve made on manufacturing in the US, that was made multiple years ahead. It happens to come in around this time, but it was made because we saw some geopolitical shifts and opportunities to manufacture in the US. But the other reason was based on a vision that said there is a need for capacity in the industry so we’re going to invest. It cannot be reactionary to every little change; it has to be based on a broader long-term industry outlook. In the last few weeks, we inaugurated an assembly facility in India, we recently broke ground on an HBM backend facility in Singapore, and we announced an expansion of our fab in Japan. Was this all a reaction to Q4 ‘25? That’s not possible; it is several things in progress that are coming together to drive the demand growth that we see.

Ian Cutress: It was last year when you guys announced $100b in US manufacturing investment over however many years. And that was even before Q4.

Praveen Vaidyanathan: Correct. We don’t have a crystal ball on everything. You have to invest based on your best understanding of the market, be closer to your customers, and then manage within that opportunity. But we do a lot of things on optimizing manufacturing using AI. Our ability to ramp new technologies has accelerated quite a bit because of the use of AI.

Ian Cutress: Pivoting to LPDDR, I know that’s going through a renaissance right now. Everybody wants LPDDR5X, but then we’ve got this new SOCAMM technology.

Praveen Vaidyanathan: Oh, do you want to see some?

Ian Cutress: This says 256GB!

Praveen Vaidyanathan: It’s a new capacity we just announced three weeks back. It’s the highest capacity low power DRAM module ever built: 256GB LPDDR5X-7500.

Ian Cutress: At GTC we saw the Vera CPU blade. How many SOCAMM modules did that have?

Praveen Vaidyanathan: It’s eight per CPU. So per CPU, you could get to up to 2TB. And if you have eight of them, then you get to 16TB of DRAM.

Ian Cutress: In this workload environment, some are demanding massive amounts of capacity and others are asking for faster memory. How do you approach that?

Praveen Vaidyanathan: Let’s take an example of SOCAMM. When we announced this, we actually have a portfolio that goes all the way from 48 Gb to 2 Tb, and it has speeds ranging from 7500 MT/s to 9600 MT/s. Somebody who doesn’t want all the capacity but wants maximum bandwidth would get a 48 Gb 9600 MT/s. Somebody who wants capacity would go for this because they don’t value speed as much. LPDDR in the data center is only two or three years old for CPUs. It’s been in the mobile space for a long time. It’s been in Hopper and Blackwell architectures for some time, but it was always attached to the GPU. But now there’s a push for a CPU-only solution. With agentic AI growth, that broadens the portfolio you need. We’re okay with a single point solution for a single point application, but now we need a broader portfolio with multiple speeds. It’s a learning experience; we have a broad portfolio so that we can investigate every use case. Customers may try something and then change their mind.

Ian Cutress: In the AI space where people are selling rack scale systems, are they mostly after capacity?

Praveen Vaidyanathan: I think it’s two things. If I think about a GPU-CPU configuration, you’d rely on the HBM for bandwidth. You want that to be as fast as you can, but you can’t put everything on the HBM. So, you need to offload, the KV cache and all that fun stuff. That’s where capacity comes in. You want to make sure the memory bandwidth is not slower than your interconnect bandwidth. As long as you get that, capacity is king. So that is a minimum requirement; beyond that you want capacity. Now, if you go to CPU only, I think everybody wants everything.

Ian Cutress: We’re starting to hear the first cues of LPDDR6 coming in. I think production is maybe sometime in 2027. What does LPDDR6 bring to the table?

Praveen Vaidyanathan: When LPDDR5 was designed, it wasn’t designed for the data center; that was an afterthought. Nvidia wanted to do it, so we worked with them to figure out how we can build this for the data center. We actually retrofitted some features in there for RAS and monitoring. With LPDDR6, you can do that from the start. It’s designed for the data center.

Ian Cutress: So we should consider LPDDR6 as a fundamental rearchitecture of the memory?

Praveen Vaidyanathan: It is architected for traditional consumer applications but also for the data center. We had an opportunity to think ahead and put in capabilities that will help data center adoption. Also, SOCAMM started as a proprietary solution, but now SOCAMM2 is an industry standard solution, which helps adoption. We think LPDDR6 will go the same way.

Ian Cutress: Part of the idea of SOCAMM is that you now have modular LPDDR. But how often are you seeing partners replace the SOCAMM? Whenever I see it, it’s in a liquid-cooled system. If you wanted to change it, you’d have to get into the guts of the system.

Praveen Vaidyanathan: This is just going to the market now, so we haven’t had experience with that. Most solutions, whether you use a capability or not, having the capability provides optionality for customers. It gets more complicated with tray-level systems, and servicing them is a different problem our customers are dealing with. But having the option tells them that they do not have to scrap an expensive tray because of one chip.

Ian Cutress: Could there be a consumer GPU with SOCAMM style memory in the future?

Praveen Vaidyanathan: I think so. There’s something called LPCAMM2 that was built for PCs and notebooks. There’s nothing stopping this module from being adopted in other solutions; it’s all about designing it into the space. But they do design a lot of down-memory components to get around the “I don’t need all this”.

Ian Cutress: There are motions about whether GPU vendors sell the memory with the ASIC or whether they want it to be flexible with different SKUs.

Praveen Vaidyanathan: The nice thing about this is this form factor doesn’t change with capacity or speed.

Ian Cutress: Do you have to do anything special about power?

Praveen Vaidyanathan: We have voltage regulators on here to do the conversions to come down to the levels you need for LP, because LP runs at lower voltages, so there is power management built into the module.

Ian Cutress: Can people design LPDDR5 and LPDDR6 in the same ASIC? Or are they too different?

Praveen Vaidyanathan: It can be done. You have to design the ASIC to manage both IOs and protocols. But there are fundamental differences. For example, the LPDDR5 IO was built to be 16-bit or 32-bit; LPDDR6 is a 24 or 48-bit IO. That’s a fundamental change.

Ian Cutress: Looking to the future, how far in front are you guys prepping for the next generations of memory? Companies talk about five to seven years of pathfinding; is it any different for a memory company?

Praveen Vaidyanathan: It’s very similar. There is technology pathfinding and then there’s design/architecture pathfinding. Technology pathfinding tends to be longer. So for us, that five to seven years probably applies even more simply because of the technology pathfinding we have to do. We talked about 12-Hi HBM4, but we also announced that we demonstrated a capability for 16-Hi HBM4 to prove technology capability so that when we need it, we are ready.

Ian Cutress: I’m waiting for HBM to have just as many layers as Flash! In the 80s we talked about KBs of capacity; now we’re talking about GBs. I’m sure in 10 years we’ll want hundreds of terabytes. What should people who follow Micron know about what 2026 looks like for you?

Praveen Vaidyanathan: You should see a full portfolio of memory and storage playing into every part of accelerated compute. We talked about HBM4, SOCAMM, and we also announced that we are first to market with our PCIe Gen 6 SSDs which are super valuable as KV caches expand. We want to be a product-first, technology-first company that is there with the right solutions ahead of time.

Ian Cutress: Do you have a lead customer you partner with for each new generation?

Praveen Vaidyanathan: Sometimes, and it’s a strategic choice. When we brought LP-DRAM into the data center, our partner was Nvidia. Sometimes its a smartphone vendor. Our customers are competing in the marketplace and we want to give them the maximum flexibility to win.

Ian Cutress: Are you all sold out for ‘26?

Praveen Vaidyanathan: I think we’ve publicly said that ‘26 is all accounted for.

Ian Cutress: Sounds like a good place to be in!

Praveen Vaidyanathan: To what we talked about earlier I realised you mentioned a $100b investment, but we actually talked about $200b being invested in the US. It continues to be a commitment to how we plan for capacity for ourselves and for the industry over the next decade.

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More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, AlphaSights, Applied Materials, Arm, Armari, Arteris, ASM, Ayar Labs, Baidu, Bolt Graphics, Cadence, Credo, d-Matrix, Dialectica, Facebook, GigaIO, GIM, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, Marvell, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Rebellions, SiFive, SIG, SiTime, Supermicro, Synopsys, Tensordyne, Tenstorrent, Third Bridge, TSMC, Tsavorite, Untether AI, Ventana Micro.

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Correction: IBM is going to be using the High-NA EUV machine at Albany NanoTech, not buying their own.

There’s a reason why I keep asking high-profile executives and architects at major semiconductor companies about whether they think Moore’s Law, the process of improving transistor density*, is still in the works. On the one hand we’ve got Jensen at NVIDIA saying that Moore’s Law is dead, joined in part by Huawei but only simply because of not having access to the latest tools. On the other are AMD and Intel who recognise that Moore’s Law is part of the ongoing evolution and still remains a critical part. In the middle is TSMC, who in the words of Deputy Co-COO Kevin Zhang, told me ‘I don’t care.’ So who is correct?

When it comes to IBM, I firmly believe they’re in the camp of saying Moore’s Law is still alive. Four years ago, in 2021, the company announced it was the first to achieve a scaled Gate-All-Around (GAA) transistor design in a number of test vehicles between full logic and memory designs. This was substantial, as Gate-All-Around technology had been earmarked as the next stage beyond the FinFET designs that are common in the industry since 2012. IBM referenced the technology as a ‘2nm-class’ design, and while the only direct licensee of its technology is Rapidus in Japan, it paved the way for a wealth of Gate-All-Around designs to start hitting the market this year, in fact. While TSMC, Intel, and Samsung developed their own equivalents, IBM was proud to announce itself as the first.

Fast forward to 2026, and IBM is set to do it again. The transistor roadmaps from the leading research houses (eg imec) have earmarked that beyond several generations of FinFET then several generations of Gate-All-Around designs, the industry would pivot to a new design called CFET, or Complimentary FET. Instead of scaling transistors across a chip in a two dimensional way, CFETs enable a form of stacking, enabling more transistors in the x/y plane. There are multiple types of CFET design in the literature, and specifically IBM has built a staggered sequential CFET design. More on that later in the article.

IBM has dubbed its new technology with a marketing term: NanoStack. The baseline numbers look kind of mindboggling, similar to what we saw with the move from FinFET to GAA.

• 50% Logic Area Scaling

• 50% Performance at iso-power

• 70% Efficiency at iso-performance

• 40% SRAM scaling

• 666 Million Transistors per Square Millimeter (666 MTr/mm²) *

In these numbers, IBM is compared to its own 2nm process technology.

*The 666 number comes from IBM’s press release that states ‘100 billion transistors in the size of a fingernail’. IBM said half that number in a fingernail for its previous 2nm, and we got clarification they meant approx 150mm². So 100 BTr / 150 mm² = 666.66 MTr/mm². There’s a better number later in the article.

IBM expects the scaling of the process to take around five years before this technology hits the market. IBM stated that the ‘expected markets who can take benefit’ of the technology would likely adopt it first, and based on current macroeconomics and chip design methodology, that’s still likely to be smartphone or small AI chiplets.

The company also states that this technology would benefit from High-NA EUV to reduce the number of patterning steps on critical layers. However it should be noted that it isn’t technically needed - IBM is currently in the process of waiting for the High-NA EUV tool at Albany NanoTech to be installed and they’ll use that.

In the rest of this article, we’ll go into the details we know about the technology, as well as some pre-amble to ensure we’re all on the right level.

The Transistor Roadmap

One of the best ways to understand what’s coming down the pipeline from the big players in terms of transistor design is to look at what’s happening in the research conferences and from the research institutions. Over the last decade leading up to the productization of the latest transistor technology, there are lots of research papers and presentations about work being done to build and develop what’s in the roadmap. What is in the roadmap? Well it up to now the transistors have gone through this.

On the left is the Planar transistor, which was the main method for building transistors all the way up until the 2010s. It still is the base design for all chips built at 22nm and above, and is comparatively the simplest design, however it is the reason for a lot of advancements in this space. As we shrink a planar transistor to fit more on a chip, if we shrink them too much then the source and drain become too close causing electrons to leak, and the design reaching electrostatic limits as they shrank.

The FinFET transistor in the middle solved that issue. By extracting the source and drain up out of the substrate and wrapping the gate around it, this lead to better electrostatic control and conducting channels on three sides, rather than just the one. This leads to an increase in drive current for higher performance. Multiple generations of FinFET shrank the design but increased the height of the fins, to maintain balance. As scaling continues, tall fins become fragile to manufacture and the ‘fourth’ side of the fin without a gate is overpowered by the electric field. Not only that, but another way to increase density was through fin depopulation, using only one or two fins per transistor, which reduces drive current and switching speed.

This led to the Gate-All-Around design. By wrapping the gate all the way around the channel, the result is better control and current flow. Instead of ‘fin depopulation’, designers can control the number of layers in their gate, as well as the gate width, in order to fine tune the performance and power needed for a given cell or cell library. The complexity of gate-all-around comes from the need to build the layers or ‘sheets’ - while they look simple enough in this diagram, each one needs to be surrounded by a protective layer, and the steps to do that rely on some interesting chemistry and physics. The sheets themselves may only be five nanometers thick (so, 15 atoms) with a few atoms of protective layer, but the sheets often vary between 20 and 40 nanometers in width.

In the design phase of Gate-All-Around, we saw a wild array of approaches from the main players and research houses. Firstly around getting it to work in the first place, then designs from 2 sheets up to 7 sheets, with the materials and spacing being fine tuned. The first GAA silicon is now currently on the market as of late 2025, with:

• Intel is using a four layer design branded ‘RibbonFET’ in its 18A process node technology (Clearwater Forest, Panther Lake, Wildcat Lake).

• TSMC is implementing GAA in its N2 node using three sheets, with the first product expected to hit the market later this year with AMD and its new CPU, Venice (more on that at the end of August at their AI day).

• Samsung would argue they were the first to market with GAA in their 3nm design process SF3E in 2022, with a crypto ASIC for MicroBT. Their first mainstream product with GAA on SF2 was the Exynos 2600 mobile processor in late 2025.

• Rapidus has licensed IBM’s technology design and is currently installing tools in its new 2nm fab in Chitose, Hokkaido. It has already started running test wafers since 2025, with first product tapeouts in late 2026 and production ramp through 2027.

Here is imec’s roadmap from 2023. The process node names are a little behind, but it represents a key feature of modern semiconductor technology development.

From N7 to N3, imec highlights three generations of FinFET technology, with one of the main dimensions being metal pitch scaling.

From N3 to N2, we have the transition from the latest generation FinFET to the first generation of Gate-All-Around with nanosheets.

N2, A14, A10 and A7 are all generations of Gate-All-Around design. When we hit A10 in this roadmap, the gap between consecutive NFET and PFET gets replaced by a barrier to enable them to be closer together - this has been dubbed ‘ForkSheet’ in the literature but most players now just call it an updated version of GAA. Then we move into CFETs.

The point here is to show that each fundamental transistor design is built with several generations in mind, allowing for low hanging fruit improvements before a big pivot to something potentially a lot harder, with a lot more steps, or simply because the research hasn’t been done or the material science needs to happen. It takes a long time to do any of these steps, and hundreds of thousands of people. Not only the transistors but power delivery, metal stack design, and everything else.

It means that when I show this image above, each one of these steps can be seen as a multi-generational effort, and not simply one after the other. CFET also comes in a variety of designs, has its own multi-generational effort, eventually leading to 2D transistors using Transition Metal Dichalcogenides (TMDs) like molybdenum disulphide (MoS₂) and tungsten diselenide (WSe₂). We’re expecting that announcement in 2031. That was a joke.

CFETs Normally Come in Two Flavours

On the face of it, given the image above, a CFET looks like a silicon designer’s dream. Overnight, it’s an immediate doubling of density compared to GAA. IMMEDIATE. I mean, look at that diagram - since whenever has a diagram been misleading?

Let’s start by mentioning at least some of the research that has led up to CFET. Technically by the definition of NMOS over PMOS as in the diagram, it’s not always necessary that the two parts have to be GAA, i.e. GAA on GAA. Over the last five years we’ve seen research from Intel and others showing one Fin on one sheet of GAA, Fin on Fin, and maybe even planar in the mix. That’s simply because planar and fin are well known processes. A lot of this research was also done at larger nodes too.

However in the last 3 years or so, we’ve seen more efforts for two-sheet GAA on top of two-sheet GAA, and the evolution of that. Ultimately production level CFETs are expected to be 3-on-3 or 4-on-4 or a mix in between.

But truth be told, there are two main ways that the industry has been looking at even building these designs. We call them monolithic CFET and sequential CFET.

Monolithic CFETs (mCFET) have a clue in the name. Much like a multi-sheet GAA design, a monolithic CFET will build all six to eight layers on one piece of silicon, then do the etching/plating/filling as necessary. There’s some additional control needed to enable that, but broadly speaking it’s as complex as building more layers onto a GAA design. The top line benefits of such an approach are meant to be simplicity and density.

A lot of work is being placed into mCFETs to ensure performance, yield, and scale. One of the main issues is the restriction on process steps as the stack is built higher. Because pMOS and nMOS have different materials that build them, any step to build the nMOS on top of the pMOS (and vice versa) cannot interfere with what is underneath. So you can forget that 1400ºC annealing step and spend years trying to research a new way that is as good, as cheap, and as scalable.

Sequential CFETs (sCFET) instead bond together using two or more wafers. That’s a relatively easy way of looking at it, but there are multiple methods.

1. One, each wafer has a set of GAA devices on them, either all nMOS or all pMOS, and with some clever physics, are bonded together such that they connect in the right places with the right overlay and act like a CMOS transistor pair. The benefit of such a design means that each type of transistor can be heavily optimized without worrying about the effect on the other - even more so than a traditional GAA or FinFET design.

2. Two, the first wafer has a set of GAA devices on them, and the second carrier wafer brings over some structures for the upper tier and the rest of the design is fabricated on top. This is a stop gap to assist with specific device optimisation, but still needs careful planning to deal with thermal integration as mentioned above.

The downside is the bonding - it has capacitance and a margin of error, and any slight deviation makes both a lot worse.

There’s an interesting discussion as to which process might be more expensive. On the one hand, mono-CFETs have additional layers on the same wafer, leading to cascading yield metrics on a single piece of silicon. By contrast, sCFETs can only need half the number of sheets on each wafer, but the cost comes from the bonding accuracy and yield loss. In the diagram above, imec is showing three generations of sCFETs and how the bonding between them evolves.

Which one of the two is better is hard to say, and will depend long term based on the research. Again, if we’re looking at 2031 for the first CFET designs to hit the market (we still have 3-4 generations of GAA first), then how those designs are improved and research will determine which ends up better. An old report from SemiAnalysis in 2024 claimed that all the leading fabs were primarily looking at mCFETs.

IBM’s CFETs Are Wonky By Design: Part 1

Instead, IBM is going down a third route.

It has been known for a while that NMOS and PMOS transistors prefer different orientations of silicon atoms. If you’re wondering how silicon has different orientations, it’s all to do with the lattice inside and if you were to cut it in a specific direction, where exactly you would cut it.

The green lines are where you would cut an infinitely repeating crystal. So on the left, a cut into silicon in the (001) plane would give you five atoms in red direct, whereas in the (110) would give you eight atoms in red. You can cut in any plane, such as (010) or (101) or (011), but these are the two that matter in this context.

It turns out that for transistor performance, NMOS transistors prefer (001), and PMOS prefer (110). What this means is the “mobility of the conducting element” in each transistor type is improved by the different silicon orientation. If you’re also wondering why I worded it that way and didn’t simply say mobility of electrons, it’s because NMOS uses electrons but PMOS uses electron holes. It’s a material science thing that works, and the mobility of each matters, but is beyond the scope of this article.

The problem with needing two different silicon orientations is that in a monolithic design, you are limited to one or the other, at least in planar and FinFET transistors. You could technically grow silicon epitaxially in the right orientation in the right spots, but it’s often difficult, time consuming, expensive. As a result, most wafers prioritize the NMOS transistors, hoping the PMOS performance is up to par. Over the years, additional strain to the channel has also been created artificially to improve performance. In FinFETs, because there’s an additional side in the design, technically the channel is exposed on two planes, which can be beneficial.

In Gate-All-Around designs, you also have two planes, except now the sheets are long rather than tall, emphasising the (100) plane loved by NMOS. Again, strain is also added through the silicon-germanium liners around the sheets to improve performance.

In sequential CFETs, there’s now an opportunity to use two different wafers with two different lattice orientations. This is one part of what IBM is doing.

The manufacturing process looks as follows:

• Build PFETs on carrier wafer with (110) channel

• Use 2nd carrier wafer to bond on the top layers of silicon with (001) channel

• Remove 2nd carrier wafer

• Use new (001) silicon to build NFETs and backside integration***

• Attach new 3rd carrier wafer

• Flip over and detach original carrier wafer

• Build backside integration on original PFETs

It looks a little like this:

Now for those of you following closely, there’s a triple asterisk in my list above and in the image. This is important, because here IBM is building the top layer of transistors in the new crystal structure. This means we have what looks like the same issues as with monolithic CFETs - one wrong high-temperature process step and the whole thing goes kaput.

IBM says they managed to solve this by using techniques inspired by 2012 gate-first High-K Metal Gate technologies to the NFETs with replacement metal gates, the problems are resolved. They showed this graph.

With conventional replacement gate methods on monolithic designs, the two numbers on the left show the effect of the thermal issues. We see here the damage it does: the threshold voltage (Vt) increases from 0.35 to 0.55 volts, and the gate current/leakage goes up by two orders of magnitude. Sometimes this is likened to a leaky faucet, but instead of a drip you end up sailing down the street.

On the right are IBMs results in solving the thermal issues in their stack - an almost similar threshold voltage (which looks pretty damn good), and an even better gate leakage.

But in short, for Part 1 of IBM CFETs Are Wonky, it’s because they use two different crystal lattice directions in a sequential CFET design.

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IBM’s CFETs Are Wonky By Design: Part 2

In their research, one of the critical limiting factors in CFET design is where you put the channel contacts. A regular CFET image doesn’t really show it that well, but both sides of the transistor need contacts for power and signal in order to work. In a purely stacked linear design, that has issues.

In this diagram, on the left, we have our three-sheet GAA transistors, each with signal and a form of backside power. That’s how some of them look today with GAA designs on the market.

In the middle is what happens when there’s a stacked design. Due to the signal and power coming in from the opposite side for each transistor and having to circle around the other part, there ends up being a lot more signalling and power to deal with. Also, due to those additional connections, the width of the sheets in a sCFET have to shrink and are limited in size.

On the right is what IBM is doing. They claim it to be a unique approach in the industry - a staggered sCFET design they’re calling NanoStack. By offsetting the NMOS and PMOS from each other, it allows for direct connectivity from either direction. This not only makes it easier to design, but allows for the sheets to have a wider range of effective widths, allowing for higher power and faster switching transistors for the target markets.

The key difference here is that diagrams of monolithic CFETs often leave out the connections on the transistors because they haven’t really been needed before when talking about density and drive current. This time however, IBM is claiming up to a 65% increase in effective gate width per 4-track cell compared to an ‘aligned’ sCFET design.

Here’s another nice image of the staggered design in their modelling software, showcasing the easier and more regular approach that the staggering allows.

The Secret Sauce: Bondage

In our briefings with IBM, they were keen to point out that this staggered sCFET design is only possible due to the unique bonding technique they have created, enabling the crystal lattice orientation changes. I’ve discussed at length on stage and on calls to clients about the differences in bonding technologies, but IBM says it’s doing something different and unique to enable this.

IBM is keeping the exact recipe a secret, but has given us hints. So I’m going to describe the problem, and what we do know. Let’s pull out a diagram that based on Huawei’s recent announcements has become popular again. It’s the 3D stacking scale diagram from AMD.

This diagram shows how tight the connection pitches need to be to enable different forms of stacking. The reason for this comes down to performance, power, and complexity. The closer to the silicon the sub-divisions of the design, the more connections you need, and thus the tighter packed they need to be. On the far left is traditional C4 bump bonding, with a bump-to-bump pitch around 50 microns, coming down to 35 nm using micro-solder balls, or 20 micron using copper pillars. Then we move to direct copper-to-copper bonding with hybrid integration on the right, going from 9 micron pitch down to 4, 3, or even 1 micron.

The thing is, even at that level we’re still only at the circuit splicing. Now, there’s a small definition problem here - what exactly would you call circuit splicing and how is it different to IP folding? Are we subdividing at the library level, the cell level, or something deeper? I tried to create something that evolved the original slide.

I actually went down a little bit of a rabbit hole on this one and got nerd sniped. The issue is that AMD’s original slide shows circuit slicing using TSVs, which are normally a back-end manufacturing process (done at the end). In order to make that work, it would actually be more like a ‘just before the true BEOL starts’.

IBM on the other hand describes its bonding process as categorically not back-end of line, with a completely different technology of doing it, enabling finer grained pitch contacts. This is because they build the NFETs into the silicon as it’s deposited, so the bond between the transistors isn’t as simple as a TSV shown in the circuit level splitting.

IBM calls what they’ve done a ‘gate merge’ design. They’re using a bonding dielectric during the front-end design process (i.e. at the start). This enables the bonding between the lower layer and upper layer to be defined before manufacturing of the top layer takes place, and thus metrics such as overlay don’t factor in like a TSV design. This is what makes us confident that IBM’s overall density numbers for transistors are more believable than Huawei’s simpler TSV IP splitting technology using older process nodes.

All that being said, IBM’s narrative in our meetings is that the bonding technology is what has enabled all of this, and that’s why it’s very special and very secret. They mention in the papers that 10 nanometers of bonding oxide equates to a 2.5% increase in cell-level effective capacitance, so reducing that as much as possible is a key dimension. At VLSI, IBM showed a sub-30 nm bonding layer, verified via scanning acoustic microscopy to be within 1.5 nanometers across a full 300 mm wafer.

The end result is a set of crystal lattice layers on the top of the wafer ready to be built into. The following image shows after the bonding, and then after building the transistors.

The end result is a pair of transistors that don’t look out of place in any other design. Usually with transistor design, one of the main metrics is how current scales with applied voltage. The magic number for CMOS designs is always to get as close to 60 millivolts per decade (per order of magnitude of current) as possible, as the lower that number the easier it is to turn on and off the transistors.

IBM scores 68-70 millivolts per decade, which considering the time from high volume manufacturing is really good. By comparison FinFETs can be from 65-85 mV/dec, and planar transistors are around 80-100 mV/dec. FD-SOI, a high-performance planar alternative, goes between 65-75 mV/dec. GAA is expected to be 60-75 mV/dec in its lifetime.

Numbers

Now let’s talk about some physical numbers when it comes to transistor cells. When designing a chip the designers work at the cell layout rather than the transistor layout.

In this table we have IBM’s 2nm compared to their 7A Nanostack, with some aligned sCFET in the middle.

The major change is the 50% reduction in track height. In a cell design, tracks are built to support signal and and power connections - IBM believes a 4T design is most efficient with their sCFET. If we multiply the track height by the metal pitch, we get the cell eight numbers.

The area proxy for a standard cell is roughly CPP multiplied by the Cell Height. This gives us:

• 2nm GAA: 6045 nm²

• Aligned sCFET: 3953 nm² (35% reduction)

• Nanostack sCFET: 2958 nm² (51% reduction)

Relative to 2nm, this is where IBM’s 50% scaling comes from.

IBM also showed off this graph:

Unfortunately no detail was given as to how this graph is calculated, although it’s worth noting this is based on transistor level metrics, not cell level, IP-level, or chip-level designs.

To be honest, I think the most impressive line is if we look at the nanosheet (6T) peak performance. It’s at 1.2 AU but using 2 AU of power. We can draw a line straight down from that to NanoStack 7A.

That’s down to a power of 0.42 AU. That’s a 79% saving. Insane.

Let’s talk SRAM Scaling

While technically most of IBM’s numbers here were published in their 2025 VLSI paper, it’s what came through the 2026 submissions that enables them to have this announcement today. One of the key limitations in transistor node scaling has been SRAM, and given the ratio of SRAM to logic on a modern processor, if it doesn’t shrink then the effect of a process node change means little to nothing. One of the prospects with CFET, given its literally stacking one transistor on top of another, means that with a perfect geometry we should see a doubling of SRAM cell density overnight. That naïve way of thinking is a good place to start, although with the additional periphery needed for SRAM control, IBM is claiming a more modest 40% reduction in cell height compared to its 2nm process. Still, nothing to be sniffed at.

Modern SRAM is compared by either cell area in square microns, or density in megabits per square millimeter - and it is usually built with the high-density process variant. Currently the leading numbers are:

• TSMC N2: 0.0175 µm², 38.1 Mb/mm²

• Intel 18A: 0.0210 µm², 38.1 Mb/mm²

• Synopsys on TSMC N3: 0.0213 µm², 38 Mb/mm²

• Samsung SF3/2: 0.0199 µm², 29.02 Mb/mm²

(data from ISSCC 2025, Kurnal Insights)

In IBM’s research, they found that the staggered sequential CFET approach actually allows them to tighten some of the transistor gate spacings for better density compared to the basic aligned approach.

The y-axis on this graph is showing bitcell height, and the x-axis is a measure of how much they can push some of those spacings. On the face of it, the smallest bit cell is 0.011 µm2. That could yield a theoretical maximum SRAM density of 90.91 Mb/mm2, however real-world density is usually around 55-65% of this number, meaning a probably real-world density of just shy of 60.

• IBM 7A NanoStack: 0.011 µm², 54.5-59.1 Mb/mm²

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On The Topic of Transistor Density

Now I’ve mentioned this once or twice before, but it’s important that it has its own section.

Historically transistor density, in its very name, should be measured by how many transistors you can fit into a given area. Since time immemorial (aka September 3, 1189), most protagonists in this space have assumed that value to mean on a singular piece of monolithic silicon, i.e. an x/y dimension limit.

Where this definition requires scrutiny is in the event of going vertical, i.e. stacking. This applies to multiple chiplets stacked together, as well as what IBM is doing with sCFETs.

To begin, I think we can agree that monolithic CFETs still fall under the original definition and are fine.

We typically do not sum up directly bonded chiplets and consider that a density increase - eg AMD’s V-cache or MI300X technologies. Each piece of silicon has its own density.

Huawei recently announced its Logic Scaling, which based on our graph would be IP folding. The company claimed that this was a density improvement, by layering cell libraries on top of one another using TSVs for more direct communication. I fundamentally disagreed, and said Huawei was extracting the urine on that one. I saw the reason why, but felt it was an attempt to pull the wool over the eyes of the general public. Given how successful commentators in this space still don’t realise that ‘3nm’ is a name and not a dimension, Huawei were hugely successful with their news. I guess that’s why those commentators get invited and sponsored by Huawei. But if we went down Huawei’s route, if I bonded five chips together at 50 billion transistors each at 100 mm2, suddenly I now have 250 billion in the same area. That’s not a node increase, that’s just urban planning.

The thing is, IBM’s not doing that. They’re still building transistors into the same piece of silicon. It’s just that what they’re building into was carried over and bonded onto the original transistors. The delineation is not through TSVs, but direct transistor-to-transistor connections that the method builds in, rather than traditional hybrid bonding. It’s within the cell library, rather than between cell libraries. To me that still counts.

So time for some math. For ease of use, I’m going to be using Kurnal Insights for some numbers.

Let’s use Intel’s/Bohr’s formula for calculating density. It uses the cell height and gate pitch to build up sizes of two of the most popular types of structures in a processor - NAND2 (memory) and Scan Flip Flop, SFF (logic). Then it uses a typical ratio of these to get the density numbers. There’s also a caveat about separating transistor regions, called diffusion breaks. Also high-performance designs will be different to high-density designs.

Huawei did a different calculation scheme. I could include those for fun.

Nonetheless, some numbers.

IBM Nanosheet 2nm

• Cell Height: 120-140 nm

• Gate Pitch: 45-48 nm

• Density: 219.30 - 272.90 MTr/mm2 * (originally reported 333 MTr/mm2)

• #HuaweiMath: 370.37 MTr/mm2

IBM NanoStack 7A

• Cell Height: 64-72 nm

• Gate Pitch: 42-45 nm

• Density best case: 548.25 MTr/mm2

• #HuaweiMath: 744.05 MTr/mm2

To put that into perspective, here are the high density numbers from current and popular process nodes.

• Huawei 2031: 400+** using HuaweiMath

• Huawei 2030: 292.00** using HuaweiMath

• Huawei 2026: 238.00** using HuaweiMath

• Rapidus 2HP HD: 237.31

• TSMC N2 HD: 236.17

• TSMC N3P uHD: 223.96

• Samsung SF2 UHD: 206.11

• Intel 18A HD: 184.24

• Samsung 3GAP HD: 182.75

• Huawei 2025: 155

• Intel 3 HD: 140.35

• Samsung 4LPP HDL 137.83

• TSMC N5 HD: 137.60

• TSMC N7 HD: 107.73

• Samsung 7LPP HD: 102.28

• Intel 10nm HD: 100.33

• SMIC N+2 HD: 92.82

• Samsung 8LPP: 60.92

• TSMC 10FF: 55.92

• Intel 14nm: 44.40

• TSMC 12FFC: 39.98

• GF 14LPP: 32.80

• Intel 16nm: 21.26

Three trends stick out.

First, what are you smoking Huawei.

Second, IBM’s best case 2nm number from 2021 still hasn’t been achieved. That might be an indication of where sCFET gets to in a similar timeframe.

Third, IBM NanoStack 7A worst case is ~382 MTr/mm2. That’s if you use the worst case dimensions and need a double diffusion break between cells. But if you take either number, it’s still a sizeable jump.

The Other Parts of the Puzzle

Between two papers, two sets of slides, and the equivalent of a few hours of questions in my hands, this is the article. There are a few more points to flesh out due to the answers of those questions that don’t really fit in anywhere. So they’re going here.

Q: What is the minimum threshold voltage? One paper shows a test at Vds of 650 millivolts, and the thermal testing shows Vt at around 350 millivolts

Answer: it’s similar to a scaled version of 2nm

Q: What material is the gate-merge interface material? Does it follow IBM’s research with Tungsten and Titanium Nitride liners as via contacts?

Answer: Cannot disclose at this time.

Q: Is IBM still researching monolithic CFETs? I know many factors go into this, like physics or economics, but in your personal opinion, what would you think has more scaling potential - monolithic CFET or staggered/sequential CFET?

Answer: IBM started on mCFET first, we called it 3DSFET back in 2014. We spend 3+ years understanding the constraints. However we developed the staggered design when we understood it offers flexibility.

The additional thing is that you stack more layers with this staggered design. Once you build signal lines and power lines into each wafer, it’s stackable, unlike mCFET. sCFET enables z-direction. Fully leveraging z-direction for transistor scaling.

Ian: Once you solve for thermals, daaaaang. IBM has a bunch of patents on that from the early 2000s. It will be interesting to see where it makes sense compared to chiplets though.

Q: The images on the slides are showing approximately 60nm gate width. Normally we see 20-40 nanometers with current gate-all-around designs. Is 60nm indicative or just representative?

Answer: When the sheet is wider, if you can fit into the density, and the performance is better. That limit in a nanosheet is by device but also due to CMOS patterning on the device stack. There are also NFET vs PFET differences. With sequential CFETs, you can do that independently compared to CFET which has to stay the same. As we’re also not limited by NFET vs PFET differences, it increases the margins in the sheet width for better optimization.

Q: Do staggered sequential CFETs have direct benefits with defect yield? A follow up - is it even possible to test the different NFET and PFETs before bonding to ensure working transistors?

Answer: We haven’t really practiced that - there are concerns with introducing tests into the manufacturing process. It took us a year to model and develop the thin dielectric bonding - but we test for thin dielectric with no wafer distortion so it’s defect free. But for testing we are looking at the idea.

Q: How do you think NanoStack would change the EDA approach to circuit design?

Answer: We’ve said that it will take 5+ years to bring this technology volume. That covers all aspects - the technology, supply chain, but also the EDA. It is time for EDA to embrace the vertical direction - it’s similar to EDA in 3DIC at the chip level, but this is the first time enabling 3D at transistor level, and EDA enablement in the next few years is critical. We also need to work with our tools partners to deal with metrology and inspection in 3D.

Q: What thermal, signal integrity, and power delivery challenges will need to be overcome for yield improvement? Do you anticipate materials innovation in those fields?

Answer: Yes to materials challenges, and 3D EDA is also related. IBM is moving away from 2D to 3D with NanoStack, but in physics, we are moving away from electrical challenges to more mechanical and thermal* challenges. We have to define the technology, the access to the technology. We are working to enable the mechanical and thermal as part of the definition of the PDK. Can think of the technology definition not just about the PPA but also the mechanical and thermal requirements. We are working with EDA partners to ensure that, especially for thermal, they’re developed and integrated in the beginning.

On the materials. Our design allows for flexibility in both NFET and PFET independently. It removes the need for limits brought about from NFET to P, or P to N in manufacturing. For example, we’re looking for new innovation for highly conductive material for vias. Bonding quality has to be high and defect free.

Q: Do we need High-NA EUV for this?

Answer: Enabling a source for single patterning metal layers is crucial for this technology. We are in the process of [waiting for the High-NA EUV machine to be installed at Albany NanoTech] to test these limits.

Ian: What’s funny is that answer categorically indicates that no, you do not need High-NA and it can be achieved through multi-patterning. Because this is more like stacked GAA, the critical dimensions aren’t changing that much, so that makes sense, however with some of the cells being fewer tracks and everything, High-NA here will likely condense multiple patterning EUV steps into one, making it easier on cost and yield long term.

Conclusions

IBM’s NanoStack announcement is one of those rare process technology disclosures where the more closely I look at it, the more WTF my face contorts until I understand it. It took a good couple of hours before I realised it wasn’t simply two sets of wafers stacked on top of each other, for example, and more of a crystal lattice carrying and etching process.

The staggered design addresses the very real problem of getting power and signals into the devices, while the use of different silicon orientations gives the NFET and PFET layers room to be optimised independently. The gate merge bonding process I’m told is the real secret, as it then ties the whole thing together at a level that still feels like transistor scaling rather than simply packaging dressed up as a process node.

In terms of numbers, the highlights carry far and wide - a doubling of transistor density into the 500+ range, and a sizeable jump in SRAM density as well. If the raw cell power and efficiency numbers are to be believed, then you can have the highest performing N2 cell on 7A at only 21% of the power. It almost sounds like sequential CFET can’t get here quick enough.

But none of this means IBM has solved CFET manufacturing. The process still needs to survive the transition from research wafers to high-volume production, and the bonding itself needs to become rock solid and reliable. Inspection, defect management, thermal modelling, power delivery and mechanical constraints all become more difficult once transistor design moves into the vertical direction.

The EDA problem I brought up in the Q&A does weigh on my mind, as someone who works closely with Synopsys and Cadence. NanoStack requires design tools to understand not only conventional timing and power, but also the mechanical and thermal behaviour of a vertically integrated cell. IBM says this work will be developed alongside the process and incorporated into the PDK, which is sensible, but it also shows how much infrastructure must exist before anyone can build a competitive product with it.

High-NA EUV should help with cost and yield rather than determine whether NanoStack is possible. IBM developed the current test structures without High-NA, which means the technology can in principle be manufactured through additional patterning steps. A High-NA tool could collapse some of those steps into single exposures, especially around the tighter metal layers, but it does not remove the harder challenges around bonding, materials and thermal integration.

The five-year timeline therefore sounds reasonable rather than conservative, especially with what we’ve seen with GAA. IBM need foundry partnerships to develop the device, the process, the inspection techniques, the design tools and the supply chain at the same time. Then that foundry needs a customer willing to accept the early cost and risk, which makes a smartphone processor or a small, expensive AI chiplet a more plausible first product than a large general-purpose CPU or GPU.

What IBM has shown is a coherent path into the CFET era. The staggered geometry solves a real problem, and the sequential construction enables independent transistor optimisation. The bonding process appears fine enough due to its method to preserve the argument that this is transistor-level scaling. Now there is still an enormous distance between these test structures and commercial silicon - for example what set of Vt devices are possible for different parts of a chip design. But NanoStack now looks like one of the more credible approaches to vertical transistor scaling.

I am genuinely looking forward to being invited to Albany to taste it. See you soon Mukesh!

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, AlphaSights, Applied Materials, Arm, Armari, Arteris, ASM, Ayar Labs, Baidu, Bolt Graphics, Cadence, Credo, d-Matrix, Dialectica, Facebook, GigaIO, GIM, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, Marvell, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Rebellions, SiFive, SIG, SiTime, Supermicro, Synopsys, Tensordyne, Tenstorrent, Third Bridge, TSMC, Tsavorite, Untether AI, Ventana Micro.

• Both Samsung and SK Hynix have working LPDDR6 silicon. Just seven months after the JEDEC specification was ratified.

• The effective bandwidth at 14.4 Gbps is 38.4 GB/s per die.

• SK Hynix chased bandwidth, Samsung chased efficiency.

• The shmoo plots tell the story on where the silicon is right now.

• This is just the first generation of LPDDR6 silicon. It’s only round one, more to come

What Samsung and SK Hynix have disclosed in individual papers published at ISSCC 2026 shows that both companies have working LPDDR6 silicon, despite the standard being ratified by JEDEC only a few months ago. As progress marches on, recent ML workloads have created a demand for high capacity, high speed memory, with throughput bottlenecked in all sorts of devices. In small devices such as smartphones and notebooks, it means the memory subsystem is one of the biggest limiting factors in creating devices to run capable and up-to-date on-device models.

What both companies showed off at ISSCC 2026 is more interesting than it looks on the surface. While both Samsung and SK Hynix arrived with working silicon, they made fundamentally different decisions about where to target its respective designs and optimizations. Samsung outlined a more modest approach to speed and bandwidth, trading pure performance for power optimizations in various ways. SK Hynix, however, leveraged its newest 1cnm process node to push straight towards the 14.4 Gbps ceiling as outlined per the JESD209-6 spec. Together, the two papers give us the first detailed, independently verified look at how LPDDR6 actually behaves in silicon rather than just on paper.

The current LPDDR Family in Brief

LPDDR5 originally debuted in 2019 with a peak data rate of 6,400 Mb/s per pin, which is roughly double that of LPDDR4X. LPDDR5X followed suit in 2021 with a peak data rate of 8,533 Mb/s, then SK Hynix managed to push things to 9,600 Mb/s with what became known as LPDDR5T. Samsung eventually went one step further and validated LPDDR5X at 10,700 Mb/s on 12nm for the Dimensity 9400 platform. The table below shows the generational uplift in peak data rate and bandwidth per die from LPDDR4X all the way up to the current LPDDR6 memory.

Throughout all the generations listed above (LPDDR4X to LPDDR5X) all use a 16-bit channel, which essentially meant that the connection between the memory and the processor was the same width regardless of how fast the data rate rose. LPDDR6 changes this to a wider 24-bit channel, which is arguably more important than just the speed itself, as it means it will be difficult to build a unified controller that supports both LP5 and LP6 modes.

LPDDR6 organises its 24-bit channel as two 12-bit sub channels per die, and this has implications in how the memory actually operates. Each 12-bit sub channel handles its own data independently from the other, and gives the memory controller more flexibility in how it handles requests and allows smaller access granularity of 32 bytes per sub channel (down from 64 bytes in LPDDR5). For AI workloads that generate lots of smaller and typically irregular memory requests rather than large sequential ones, it means random memory access should work more efficiently, and thus theoretically spends less time fetching more data than the workload actually needs.

LPDDR5X bandwidth was becoming insufficient for newer AI workloads being planned for mobile devices, and the combination of the higher data rate and wider bus width directly addresses this. Running capable on device AI models requires the memory subsystem to move large amounts of data quickly and consistently, and LPDDR5X at 8,533 Mb/s (16-bit) delivers around 17 GB/s of peak bandwidth per die. LPDDR6 at its peak with 14,400 Mb/s across a wider 24-bit channel delivers up to 38.4 GB/s per die as confirmed by SK Hynix’s ISSCC 2026 disclosure. This is roughly a 2.25X improvement over LPDDR5X and more than 3X over LPDDR5.

Before moving on, let’s familiarize ourselves with what JEDEC specified last year with its JESD209-6 specifications.

What the JEDEC Actually Specified (Published July 2025)

The official JEDEC JESD209-6 specifications define a peak data rate of 14,400 Mb/s per pin, with an introductory grade starting at 10,667 Mb/s, but there’s more to things than just peak data rate. Effectively, the peak bandwidth lands at 38.4 GB/s per die as SK Hynix disclosed, rather than the 43.2 GB/s theoretical maximum you get from multiplying the data rate by the bus width.

Beyond bandwidth, LPDDR6 makes on-die ECC mandatory rather than optional, unlike LPDDR5X. This means that error correction is now performed within the memory array before the data reaches the processor. LPDDR6 also introduces Per Row Activation Counting, which defends against Rowhammer. Rowhammer is a well-documented memory vulnerability where repeated access to the same memory row can corrupt the data of adjacent rows. In addition, a new dynamic efficiency mode reduces the interface to a sub-channel during low-bandwidth operation, providing distinct power-efficiency benefits critical for mobile devices.

SK Hynix at ISSCC 2026: 16Gb LPDDR6 on 1cnm (Paper 15.7)

SK Hynix presented its 16Gb LPDDR6 at ISSCC, using 1cnm, the latest generation of its 10nm-class DRAM family. The headline numbers are confirmed directly from the die micrograph summary table in Figure 15.7.7: 14.4 Gbps per pin, for a total bandwidth of 38.4 GB/s. The chip runs on two separate voltage rails: a higher one for speed-critical data and a lower one for everything else. This is a key part of how SK Hynix manages power consumption across different operating conditions.

More distinctly, the chip itself is operating at two different voltage levels. The higher-voltage rail, VDD2C, is running at 1.025V, while the lower-voltage rail, VDD2D, is operating at 0.875V. The VDD2C is the critical part, where more power is needed to deliver that maximum bandwidth of 14.4 Gbps per pin, while the VDD2D is designed to handle everything else.

SK Hynix is claiming over 20% better power efficiency and higher per-channel bandwidth compared to LPDDR5. Running different parts of the memory chips at different voltages is a precise way to squeeze out additional power efficiency, but SK Hynix also claims a 3X increase in bandwidth over LPDDR5.

The architecture diagram above (Figure 15.7.1) provides a clearer picture of how the dual sub-channel design operates day-to-day. SC0 is the primary sub-channel, which has all of the active logic running, and SC1 mirrors it. However, in efficiency mode, the entire secondary block is powered off, with SC0 taking full control of all 32 banks. In that particular state, running at 12.8Gbps across a single sub-channel, standby current drops to 87.3% and operational current to 81.1% of normal mode. Realistically, this is the state the device spends the vast majority of its life in, which means those numbers arguably matter a great deal more than the peak figures do.

Much of what SK Hynix provides in this paper focuses on managing power at the ends of the speed range rather than simply at its peak. The CA (command and address) bus, which is responsible for telling the memory what operation to perform and where to perform it in LPDDR6, operates between the frequencies of 1.6 GHz and 3.6 GHz, which is roughly triple that of LPDDR5, as cited by SK Hynix, and this creates some real challenges in multi-rank configurations where CA pins are shared between dies.

To address this, SK Hynix splits the operating range into three frequency bands, each with its own dedicated buffers, which are selectively activated based on operating conditions. Combined with a fast CS control scheme that gates CA signal paths more efficiently at lower speeds, standby current drops by 42% at low frequencies and 19% at mid frequencies. For a device that simply sits idle for the vast majority of its time, that is ultimately where most of the real power saving lies.

The shmoo plot in Figure 15.7.6 shows SK Hynix’s power and voltage targets for the data rate. For those unfamiliar, a shmoo plot is a visual representation of where a chip passes and fails across a range of voltages and clock speeds. This gives us a much clearer picture of where the silicon itself is actually comfortable operating versus where it is simply being pushed to its limits. At 1.025V VDD2C, SK Hynix’s device passes at 14.4 Gbps, which is also the JEDEC ceiling.

Dropping the voltage down to 0.950V causes the bandwidth to fall back to 10.9 Gbps. This says that SK Hynix’s 1cnm process needs that extra voltage headroom available to operate reliably at its peak speed without the performance dropping. Without this headroom, performance drops off pretty sharply. This is SK Hynix’s first generation LPDDR6, and this isn’t unusual for a new process node, but it does paint a different picture to Samsung, which opts to trade better power efficiency for lower bandwidth.

That voltage-to-speed relationship becomes particularly important when we sit this directly next to what Samsung showed in its paper, because the two companies made very clear distinctions about where to optimize, and their respective shmoo plots reflect that.

Samsung at ISSCC 2026: 16Gb LPDDR6 at 12.8 Gbps (Paper 15.8)

Samsung presented its own disclosure at ISSCC 2026, covering a 16Gb LPDDR6 device built on its 10nm-class DRAM process. The summary table in Figure 15.8.7 and the table below directly confirm the key specifications.

That 12.8 Gbps Samsung disclosed isn’t chasing the 14.4 Gbps ceiling in quite the same way that SK Hynix is. The paper itself describes 12.8 Gbps as the JEDEC-specified minimum voltage operating point, which shows that Samsung ultimately chose to focus its engineering effort with its first-generation device on power efficiency.

The power domain split shown in the above illustration (Figure 15.8.2) is central to how Samsung achieved its efficiency targets. Rather than running everything at a single voltage, Samsung splits its circuits across two supply rails depending on how speed-critical they are. Samsung routes the speed-critical circuits to VDD2C, with peripheral and non-critical circuits to VDD2D, which operate at 1.0 V and 0.875 V, respectively.

The bar charts in the same figure show the outcome fairly clearly: read power drops to 73% of LPDDR5X, and write power drops to 78% of LPDDR5X. The DQ pins are the physical connections on the memory chip responsible for the movement of data between the memory and the processor. At high speeds, these pins switch states rapidly and consume power every time a pin changes from 0 to 1 and vice versa. Samsung also extended power gating to the high-frequency DQ (data I/O) and claims it is cutting standby power by an additional 10%.

Samsung also implemented Per Row Activation Counting, which is more commonly referred to as PRAC, and this is Samsung’s deterministic answer to the Rowhammer problem. Rather than simply relying on probabilistic refresh schemes, PRAC embeds counters on a per-wordline basis directly inside the array itself, tracking every single row activation and triggering mitigation before the threshold for exploitation is actually reached. The bar chart in Figure 15.8.4 shows the results: LPDDR6 with PRAC requires approximately five times as many attacks before mitigation is triggered compared to LPDDR5X. For a standard that is moving increasingly into automotive and edge AI territory, that kind of deterministic protection matters a great deal more than it ever did in a purely smartphone context.

Samsung’s Shmoo plot in Figure 15.8.6 (above) highlights what the voltage choices suggest: it has optimized primarily for power efficiency over raw bandwidth. Looking more closely at the Shmoo plot, Samsung’s LPDDR6 reaches 12.8 Gbps at 0.97 V, suggesting the silicon isn’t being pushed to its limits.

LPDDR6 at ISSCC 2026, SK Hynix and Samsung: A Direct Comparison

With Samsung and SK Hynix and its respective LPDDR6 designs, it’s worth noting that we can’t directly compare power efficiency. SK Hynix reported a 20% overall power efficiency compared with LPDDR5, whereas Samsung disclosed 27% better read and 22% better write performance compared to LPDDR5X. Both companies provide different metrics and baselines, which makes a direct comparison difficult here.

The table below pulls its figures directly from the two primary papers. Where data was not explicitly stated by either company, we have simply left it blank rather than filling in the gaps with figures from secondary sources.

LPDDR6 at ISSCC 2026: The Overall Picture

Both companies brought working LPDDR6 silicon to the stage, and both within just seven months of the standard being ratified. In addition, Samsung and SK Hynix are jointly working with JEDEC on the LPDDR6-PIM standard reported by TrendForce as of December 2024, which would integrate computational capabilities directly into the memory itself rather than relying on the host processor.

What both Samsung and SK Hynix disclosed at ISSCC 2026 gives us the first real look at its respective LPDDR6 designs and where they are currently focusing their efforts; SK Hynix on more bandwidth and Samsung on power efficiency. SK Hynix’s Shmoo plot shows voltage sensitivity on its first-generation 1cnm silicon. As the process matures, these margins will likely improve.

On process node maturity, Samsung’s 16 Gb die measures 44.5 mm², with a density of 0.360 Gb/mm². Samsung did not specify the specific node its LPDDR6 silicon is built on other than the 10 nm-class DRAM process. This could be 1a (1st gen), 1b (2nd gen), or 1c (3rd gen), with the 1c being the equivalent in SK Hynix’s 1cnm. SemiAnalysis concluded in their ISSCC 2026 roundup that Samsung’s LPDDR6 is more likely to be consistent with its 1b node than with the latest generation. The dual sub-channel architecture does add area, which partially explains the lower density, so a direct comparison of density with a single-channel design is complicated.

Each of the papers is well worth reading in full, but I expect both SK Hynix and Samsung to push further up the speed curve on their respective manufacturing processes. Both are first-generation LPDDR6 silicon, so the second time around could look very different.

Some Additional Thoughts

Section from Ian

In speaking with vendors at Computex 2026 this year about DDR6 and LP6, they stated that the difference between the two standards isn’t going to be as big as DDR5 and the LP5 variants, which may lead to unified designs across DDR6 and LP6 in silicon. While that doesn’t matter much for devices that will use LP6 anyway, it does mean that hardware that normally uses DDR might have an easy route to an LP6 installation depending on market volumes. One vendor said to me that it will really depend on whether DDR6 or LPDDR6 will hit the market first, and if there’s a lop-sided volume element.

But also, with the increased demand for CPUs and in general Arm CPUs using LP memory, we might see a shift also from the x86 vendors to an LP design at scale. For GPUs, AMD has already shown its next-gen AI chips in renders using both HBM4 and LP5X as a tiered memory hierarchy, just to add to the mix. Intel’s new Crescent Island AI inference PCIe card uses up to 480 GB of LP5X per GPU.

In terms of timeline, the DDR6 standard should be ratified this year, leading to first consumer products in 2027 and then ramping in the 2028/2029 timeframe. LP6 should ramp slightly faster than that. Normally with a memory transition we talk about the crossover point from one standard to another, usually driven by pricing. In today’s macroeconomic environment, all bets are out the window, and each of the memory vendors is simply trying to (a) make as much as they can and (b) offer something that off the shelf has a higher performance/density at 100% yield than their competitor. What’s driving the new standards is that the compute needed wants the performance, density, and power improvements.

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In speaking to the memory vendors too, it’s no surprise that 2026 volume is sold out, 2027 is sold out, and it looks like 2028 is going that way fairly soon. It will be interesting to see that effect on the new generations of technology, if that’s a help or a hindrance. We have an upcoming interview with Micron later this week, so please stick around for that.

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

In terms of a history lesson, for decades, much of that timing market was built around quartz based devices. We’d cut and polish crystals to hit given frequencies. But as modern systems have become faster, smaller, more power sensitive, and more demanding in terms of resilience and precision, timing has had to evolve with them. That is where MEMS based timing comes in.

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Instead of relying on a quartz crystal, companies like SiTime use silicon based Micro ElectroMechanical Systems to generate highly precise frequencies in a form that can be tuned, ruggedized, miniaturized, and optimized for a much broader set of use cases. That matters more today than ever, because of the growth of AI infrastructure. Not just the compute chips, but the optical networking especially is a big focus for the years ahead. There are also the autonomous systems, industrial platforms, and next generation communications that are increasing the need for better timing.

Joining me for this discussion is Rajesh Vashist, CEO of SiTime. I have covered the timing industry and SiTime before in 2024, but this conversation is an update on where the market is now, why timing is becoming a more visible part of the semiconductor story, and where SiTime sees its opportunity as demand rises for higher performance and more differentiated solutions.

In this interview, we talk about why timing is still unfamiliar to much of the wider chip audience despite being essential to every major system, where the current growth is coming from, how MEMS timing differs from traditional quartz, what AI and optical infrastructure are doing to demand, and how SiTime is thinking about competition, product development, and its planned expansion into broader clocking solutions.

The following is a transcription of the video interview, modified for readability.

Ian Cutress: This whole concept of MEMS’s timing isn’t new. As far as I’m aware, it’s been in smartphones for at least a decade in some form or another. Why is it important beyond what I’ve just said? Why is it important, particularly now?

Rajesh Vashist: It’s all about the importance of timing. When we went public in November 2019, it was still a fairly unknown market.

Most of the chips in the market are GPUs, XPUs, memory, Wi-Fi, and communications. That’s a big business. SiTime is in the timing business - which is an $11-12 billion market and it’s been growing 5-6% every year for the last 60-70 years. Timing is the heartbeat of all electronics, and the timing chip produces a frequency. Whether it’s a GPU or a CPU or a memory, it uses that to turn on or off at whatever level of performance that is needed.

So SiTime saw an opportunity almost 20 years ago to replace quartz with a semiconductor MEMS solution. MEMS means “micro electronic mechanical system”, which means essentially they’re moving parts but they’re moving in silicon. By definition because it is silicon, and because it’s one of the world’s most purest elements, brings a lot of technology to it. So we focused on it a long time ago. We competed with a lot of people, we beat them. We see more competition coming. But as of now we are the market leaders in these timing chips.

Ian Cutress: Whenever I see the diagram, I always remember like a butterfly vibrating its wings but at a constant beat. The devices in silicon actually kind of look a little bit like that don’t they?

Rajesh Vashist: They do! And ours are infinitesimally small. So when they’re packaged in the resonator, the chip is 0.5 by 0.5 mm. That is a packaged chip, and inside that is the vibrating element that you’re talking about, and this is 0.4 by 0.4 mm. It vibrates millions of times a second, at a Megahertz rate, and it does it for 30 years. That’s a minimum requirement for SiTime. So it’s incredibly resilient. There’s a lot of material science that goes on, there’s a lot of electronics that goes on, and we bring a lot of secret sauce in how to manufacture them.

Ian Cutress: The latest generation CPUs, GPUs, XPUs, and networking, where we’re dealing in gigabits or terabits per second- a portion of that market still uses quartz. Where do you see that going?

Rajesh Vashist: So we are a highly differentiated product, with highly differentiated performance, that enables a particular supply chain or resilience solution. So in other words, in our $12 billion market, we are not catering for $6 billion of it. The current solution suits them, and they don’t need the benefits we bring to the table. Out of the remaining market, we are still less than $1 billion. Last year we were $327 million. This year we’ve guided to something around 40-45% growth, Last year we were 60% growth.

My point here is that we are giving solutions that are high performance to wherever there is AI, wherever there is self driving, self-movement, wherever there is small size, wherever there are drones, or in consumer electronics like smart watches or smartphones that need a lot of performance. In general it’s a highly diversified business. We don’t have one market.

Yes, we have AI - that’s booming right now just like anything for anybody else. You mentioned going from 800G to 1.6T eventually it will go to 3.2T. SiTime is participating in all of that. We sell to probably 20 of the top OEMs in the business that are involved in that. But in AI, we sell to the XPU, the GPU, the TPU companies. We’re in the hyperscalers. We’re helping them define their architecture. We’re in the system OEMs and we are with a lot of the chip companies as well, the people who do switches and accelerator cards. So the AI business we guided last quarter that will probably be in the optical modules will probably grow by 50%. So hence it’s a lot of growth. But we also have automated driving. For example, in a Level 4 car, which is not really out in volume right now, we probably have $20 to $25, maybe $30 of content. Humanoid robotics, for when they happen, we’ll probably have, again, $20 of content. And then everything else is still a work in progress - the industrial markets, the internet of things, the consumer and so on.

Ian Cutress: Whenever I speak to a company that’s deeply embedded into the supply chain like you are, I often look at the financials and realize that most of the revenue comes from the 5-10 year old product. It is always a slow ramp with the latest generation to build to revenue. I can only assume that you’re seeing a more rapid onboarding of new products?

Rajesh Vashist: Our products used to take four-five years to ramp up, but now the ramp is down in some cases to nine months. In some cases it’s a little bit more sedate, 1.5 years. But we have consumer products that are ramping at astonishing levels within about a year to a year and a half.

Stepping back again, one of our board members sent us a forecast of the semiconductor industry going from approximately $750 billion to $1.6 trillion by 2030. 2030 is not that far away. That means the whole industry is going to grow by that much. Therefore you can imagine all these use cases are growing up and SiTime as a key player in that will definitely be involved in it.

Ian Cutress: Broadly speaking we categorize SiTime as a fab-less semi provider. So can you talk a little bit about your supply chain and how that comes about? You’re not using 2 nm, 3 nm logic processes if the end result is structures on the order of millimeters.

Rajesh Vashist: We are at heart an analog semiconductor company. This means like a Texas Instruments, like an Analog Devices, but that uses MEMS technology to build different systems. So our MEMS technology is made by Bosch. Bosch, in days of old, used to be an investor in SiTime and they’ve been a partner since I came on board in this company in 2007 before we had shipped any product. They’ve been a partner of SiTime since 2007 and maybe even a little bit earlier. They have a factory near Stuttgart where we manufacture all our MEMS. It all comes from there. They’re fantastic partners, and cutting edge. They do other MEMS technology and even though they’re not a merchant fab, it’s very helpful to us. They’re a little bit expensive but still really good for us. So that’s the MEMS part.

On the analog front, we rely heavily on TSMC. We always have, and as you said we’re not using 2 nanometers we’re using 180 nm, 150 nm, 65 nm. So what happens with that is it’s a little bit better, certainly cheaper (than leading edge). Then the tools that we use to design those products are not as expensive - tapeouts are significantly cheaper.

So these are building a MEMS product which is very craft oriented and an analog product which is very craft oriented, and putting the two together and making a small subsystem out of it for timing, for a customer. Because at the end of the day the customer has a timing problem and SiTime has set itself the task of solving these tough timing problems. Right now we solve it for the super big customers, but we also want to solve it for the long chain of people, our 100,000 customers, small OEMs who understand timing even less. So we focus on one thing and one thing only. We sing one song, but we sing it very well!

Ian Cutress: It’s interesting that you mentioned Bosch being this extensive manufacturing partner because at one time they were also a competitor?

Rajesh Vashist: No, they were actually never a competitor. You may recall they do other MEMS, they do gyroscopic MEMS. They do IMU MEMS but they were never “in time”.

Ian Cutress: So what does the competitive landscape look like? Because the material you feed me on a frequent basis describes something like a 2 year or even longer advantage over your competition.

Rajesh Vashist: I’ve been using that 2-year message on a rolling basis! It seems every year it’s two years away, so make of it what you will! But back in 2011-2012, SiTime competed with companies like Maxim, now ADI. We competed with Silicon Labs, now Skyworks. We competed with IDT, now Renesas. There were also a bunch of five or six small startups just like us because we were a startup. Luckily we were able to do better than all of them and they exited the business because they couldn’t handle it. Somebody gave me a number the other day that SiTime has invested close to $800 million in R&D. That’s what it takes to get this done. So if some competitors, maybe TI, maybe Analog Devices, maybe Murata, maybe ST. They might have plans to enter this market, but that’s at least half a billion that they’re going to have to spend to get into the business.

Ian Cutress: Coming from the outside, somebody who doesn’t come from timing, but has used it extensively in things like overclocking and such - that does sound like a lot of money for R&D!

Rajesh Vashist: It is! First of all, in MEMS alone, we have three ways to spend the money.

We have to build a process technology that is ours. Bosch doesn’t have a technology - it’s a SiTime technology we use in their fabs. We own the IP for the entire process, and we’re developing the sixth generation of that. So that means we have to develop it while we’re running it, while we’re running the fourth gen and the fifth gen. We’re developing not only the sixth, but also the seventh gen and eighth gen. So we have multiple process technologies that are running just for MEMS.

We also have the design of new MEMS. So that’s of course a big thing. That defines our products.

And finally we had to create our own EDA tools, our own design environment. We decided that we couldn’t find a design environment like a Cadence, like a Synopsys, like an Ansys, to do the job that we wanted. So we roll our own.

Rajesh Vashist: We have these three ways, but that’s just the MEMs.

On the analog side, we do our own design. We do our own layout. We do our own tapeouts. And these are some very cutting edge. For example, jitter as a metric. SiTime is already at 35 femtoseconds of jitter - we intend to get down to 15 femtoseconds. These are amazing numbers while at the same time keeping low power and small size. Putting these in packaging, like our OCXO packaging in our Epoch product - a package with two analog chips and three MEMS chips. That took more than a year to develop. For that design, we also have to do our own simulation because of thermal requirements and so on. That’s just in the technology part.

Then you go into marketing and sales. We try to hire people with a history of the timing market, but most of them haven’t ever sold a very distinguished or differentiated product like ours. So they didn’t know how to sell it. We’ve trained our own team to sell it.

Ian Cutress: You mentioned Renesas a little bit earlier and you’ve just started an acquisition on some of their business?

Rajesh Vashist: So while we are a clocking company and we do clocks which go in our oscillators along with our MEMS, we don’t have the same history as the other clocking companies who build it all together. We’ve always wanted to go to a customer, any customer, and give them the resonant frequency, the oscillators, and resonators, and also the clock all together.

We do that in a modest way today because we have got about 50 clocking products, but with Renesas we get 500 clocks. That’s a business which used to belong to IDT, and for those who recall it used to belong to a company called ICS which was taken public by Hock Tan in his glory days. So that business is now coming to SiTime. That gives us the ability to give a true system level solution to our customers particularly at the high end particularly at the differentiated level. We think it’s a game changer for customers because they don’t have to do the work - they have SiTime doing the work for them to make it an integrated system - either truly integrated physically or notionally integrated.

We’re very happy with that acquisition which has not yet gotten Department of Justice approval. We hope we’ll get it shortly because we think it’s pretty straightforward.

Ian Cutress: So how many people does that bring to the company and where are they located?

Rajesh Vashist: There are not that many people because all we’re getting is the engineers and some field application engineers. So we don’t get sales, we don’t get business, we don’t get any people in the business side. So we get around 150-155 people. Some of them are in Ottawa, Canada, some of them are here in the Bay Area in South San Jose and some are in Tempe, Arizona. They used to be all working for IDT. So in a sense, we’re bringing back an American company IP and technology back to the United States from Japan. That’s a good thing.

What it does is brings us customers in the clocking space. Renesas has been an amazing partner because not only are they selling us this but we would like to be able in future to enable their microcontroller business with our Titan based products, our resonator product. Now we only have a Letter of Intent so far, we don’t have the details yet, but we’d like to do that. What I really like about this is that their CEO Toshi Shibata has decided to join SiTime on the board as a board member of SiTime. We’re looking forward to having Toshi on board.

Ian Cutress: So potentially more markets beyond the $11 billion or is that included?

Rajesh Vashist: That’s included in it, but I think again we would be in the highly differentiated part of the resonator business. The resonator business is about $4-5 billion. We’d probably carve out a fifth of it, say $1 billion of it, in the small size high performance fully systematized business.

Ian Cutress: A little birdie told me that you’re in the process of moving offices because you have enough seats?

Rajesh Vashist: We are growing rapidly. We’re going to at the end of this year after the acquisition, we’ll probably be closer to between 700 to 800 people worldwide. We have around 13 locations. But here in Santa Clara, we’re going to move into a building which was the old ServiceNow building right on 101 in San Tomas. You’ll find us easily, we’re very excited about it. And we’re also moving to new offices in the Netherlands where we have a big location. We’re in Taiwan too, and probably some others as well. We’re also getting more lab space here in Santa Clara, that’s for all the lab guys at SiTime. They’re very excited about it because they’d like to be close to it. Right now we use a little bit of off the campus lab space.

Ian Cutress: When it comes to new product development - is it de novo thinking from your side trying to develop something new, or is it more the customer coming to you asking for extra features. Where’s the push and pull?

Rajesh Vashist: It’s more of a creativity exercise inside of SiTime first, because none of our customers actually know what is possible in timing!

Because timing has been frozen for so long they don’t know what is possible. Think of a Starbucks that when it started it produced an espresso, a latte and a cappuccino. Everybody knows what they are. But then they put out a frappuccino - nobody knew that a frappuccino was possible.

So in the same way our first step is with our engineers, our business people, our marketing people, our BU people, all sitting in a room and coming up with a highly differentiated problem that we can solve which is not yet solved for our customer. In many cases it cannot be solved without SiTime. So half of our products today are products that cannot be solved without any other solution. So highly differentiated.

The other is when once we put it out there, for example the OCXO that we put out, after the initial time of “oh my god you guys have this amazing product” customers say “well could you add this, could you add that.” So think of it as a new category product that comes from SiTime that then gets picked apart in a good way and becomes a better product or variations of that product and we love that kind of back and forth.

Ian Cutress: How do I know that something I’m using has a SiTime chip in it? This is one of the problems with embedded companies like yourself. You’re in that supply chain at such a point where you don’t really get any brand recognition.

Rajesh Vashist: Somebody asked me once a long time ago - would you rather get glory, or would you rather be rich? I thought that I’d rather be rich! But you can think of it this way - highly likely anywhere where there is significant AI, highly likely where there is significant autonomy. Think of a tractor on a farm, or drones. Highly likely in things that are super super super small, like watches and heartbeat monitors. Anywhere there’s a need for resiliency in communications, you’ll probably find SiTime. SiTime has shipped close to three billion units. This year we’ll ship about a billion units. Two years from now we’ll probably be shipping 3-4 billion units a year. The more differentiated the solution the more likely we are in it. That’s another way of thinking about it.

Ian Cutress: What does 2026 look like?

Rajesh Vashist: It looks like another amazing year, like 2025. I could even say that 2027 and 2028 probably look like amazing years! I think the long story on this is that we are in a place the world has never been in. I’ve been in semiconductors for 42 years and counting - I have never seen this. By the way, other semiconductor CEOs that I know have also not seen this. This is new territory - this is a place where we are leaving a mark that semiconductors really make the world different and they enable this world of smarts, communication, greater productivity, and that’s all built on semiconductors. So therefore we see a great future for the next five years really.

Ian Cutress: If there’s one thing you want the audience to know in general about timing given that probably most of the people watching are digital what would it be?

Rajesh Vashist: It would be that SiTime has created this technology, precision timing technology and we are a category creator. And like all category creators when they start, people don’t know what they are capable of. Think of when Amazon starts with selling books. Think of early Uber. Think of early Netflix.

People don’t understand, but the company does. In other words, listen to the company because when the company says they’re going somewhere, they’re highly likely a category creator is going there.

You can read the previous interview with Rajesh at the link below.

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

• This is not a GPU, and it is not trying to be. Spyre is a 75 W single-slot PCIe inference card, designed to fit in IBM Z and Power systems.

• Spyre is already shipping in systems. This overview is a summary of a detailed technical disclosure at ISSCC 2026.

• The 8-year development timeline is real and deliberate. IBM ran five generations of silicon across three process nodes before releasing the production chip.

• The single most important design constraint is the absence of an auxiliary power connector. Every architectural decision flows from that 75 W PCIe slot limit.

• The dual-loop power management system is the most interesting technical contribution in the ISSCC 2026 paper. It is not a marketing feature because it delivers measurable throughput gains over the single-loop approach IBM used previously.

IBM presented its Spyre AI SoC solution for inference at ISSCC this year, capping off what the company describes as eight years of silicon development. The concept of Spyre dates back to around 2015, when IBM Research described starting a hallway conversation about low-precision computing. The first early prototype was shown at VLSI 2018, before most of the industry had decided that dedicated inference silicon was worth building.

The first production chip, a 330 mm² 5nm SoC with 25.6 billion transistors became commercially available in 2025 for IBM z17 and LinuxONE 5, with Power11 following at the end of the year.

The general story of the march of machine learning started with AlexNET in 2012, and the evolution ever since has been parallel tracks of hardware getting faster and more optimized, or models pivoting from convolutional neural networks to recommendation engines, embedding tables, or transformers. Models such as GPT-2 and BERT had not yet evolved into enterprise staples in 2018, and most people in the industry assumed CPUs would handle a good amount of datacenter inference well enough.

IBM, along with others, started building out its test silicon to offer a more efficient solution. Initially as a test project internally (Intel does a lot of those), Spyre would appear to be the start of a commercial success for IBM as it pairs the hardware with its systems but also for the back-end of its consultancy business.

What IBM Was Actually Building Spyre For

Before getting into the Spyre chip itself, it is worth being precise about who this is actually for, because the use case shapes every decision for a chip like this.

IBM’s mainframe customers include many major banks, insurers, and governments running mission-critical transaction processing at enormous scale. A large bank processing credit card fraud scores needs to evaluate every transaction in milliseconds, at tens of thousands of transactions per second. These heavy encoder-class workloads, primarily BERT variants and similar models, have always been the bread and butter of IBM Z’s AI acceleration, going back to the on-chip accelerator in Telum. The architecture in Telum and Spyre are more than similar, allowing workloads to migrate between the two depending if latency or performance are needed.

Spyre extends the CPU AI acceleration, adding capacity for larger and more complex models, and proper generative AI support for decoder-class workloads. This means it can keep up with their token-by-token generation and the different memory requirements, which require reliable, precise hardware that can keep up.

The key constraint baked into Spyre from the start was that the accelerator needed to fit inside its IBM Z and Power systems without the need for dedicated power infrastructure. A single PCIe slot, with no auxiliary connector, and with a hard 75 W ceiling. There are comparisons that could be made to Nvidia’s T4 or L4 class of server GPUs, as you get an idea of the design space, although Spyre ends up fitting in a rather different place within it.

Five Silicon Generations Before Production

IBM’s development approach here with Spyre is not common in the current shape of the AI industry. Most companies go from first architecture to production silicon within about two or three years - startups especially will launch their first generation silicon, for example. But IBM’s presentation claims it spent eight years and ran through five generations of test/research chips before the enterprise department decided to adopt it for their portfolio.

The 14nm half-core demonstrated back during VLSI 2018 proved the concept of a programmable dataflow architecture. A full 14nm core with a two-corelet structure followed in 2020, then we saw a 7nm four-core chip debut at ISSCC 2021, providing IBM with real-world data on crossbar bandwidth and memory latency across multiple cores. A larger 32-core on the more dense 5nm SoC with full power management was shown at Hot Chips 2024, two full years before the production chip launched commercially.

Moving from that 2024 research within its SoC to the production part is a less risky step than jumping straight from architecture to tape-out, and that is precisely the point. With an architecture now capable in tapeout, the enterprise team were able to add the RAS features needed to make it suitable for IBM’s high-performance portfolio.

The Spyre SoC Architecture

Looking at the finer details within the Spyre SoC’s architecture, it has 32 active AI cores arranged in an 8x4 grid, plus two spare cores dedicated to yield.

This means theoretically that if one or two cores fail during manufacturing, the chip can still ship as a full 32-core part. All 32 active cores are connected via a bidirectional ring bus, and the full core array carries 64 MB of on-chip SRAM.

Each AI core is split into two corelets, each with 2 MB of L1, and each corelet contains a 2D 8x8 SIMD-systolic array of 64 low-precision math engines that handle the bulk of the matrix multiplication and convolution workloads. Alongside the 2D array, there are 1D vector arrays with FP32 capability that are used for activation and normalisation functions when lower-precision formats are not accurate enough. Supported formats include FP8, FP16, INT8, and INT4, which cover the quantisation options that typically matter for modern inference across both encoder and decoder model types.

According to IBM’s disclosure, the Spyre SoC’s peak throughput sits at

• 98 TOPS at FP16,

• 157 TOPS at FP8,

• 315 TOPS at INT8, and

• 629 TOPS at INT4.

IBM compares the chip to NVIDIA’s 72 W inference card, the L4. Spyre’s peak is 315 TOPs at INT8, for 4.2 TOPS per watt, rather than the L4 which has a peak at 242 TOPs at INT8, for 3.4 TOPS per watt.

IBM’s own data disclosed at ISSCC 2026 takes it one step further, claiming 2 to 3x better power/performance than GPUs using encoder-class models, though those figures are measured on IBM’s specific workloads and aren’t using a cross-benchmarkable metric that can be directly compared.

Moving on to the memory subsystem, the design choice is driven entirely by the 75 W power constraint. While HBM offers the level of bandwidth throughput engineers typically want at their disposal, it draws too much power and requires more complex, and expensive packaging that simply does not fit within Spyre’s budget. IBM went with LPDDR5 instead, with 16 channels running at 6.4 Gbps, delivering 204 GB/s of peak bandwidth and 128 GB total capacity per card, with SECDED ECC protection for all of that available DRAM. The 8 dual-channel LPDDR5 modules sit on the PCIe card alongside the SoC itself and aren’t packaged on top of it, or within it.

That 128 GB figure is also an important number in the generative AI discussion. Compared to the NVIDIA L4, which only has 24 GB..

PCIe connectivity is Gen5 x16, giving 64 GB/s of host bandwidth in and out. The RDMA engine is also worth noting, as it allows multiple Spyre cards to transfer data directly between each other over PCIe without any host CPU involvement, which is how multi-card scaling works without turning the interconnect directly into a bottleneck.

How IBM Spyre Deals With Power Management

Spyre’s dual-loop power management system is the most technically interesting part of the overall design. AI inference workloads have a highly variable power profile, and INT8 matrix multiplications can push the power and stress on the circuits.

By using compute design enabled for low voltage operation, the idea is to extract efficiency out of the design. 0.55 volts as a voltage minimum on compute IP for a modern process node is really low, almost DSP levels or even bitcoin ASIC levels. Modern high-performance IP often sits around 0.7 volts to 1.1 volts and the power scales with it. Designing low Vmin circuits is a skill in-of itself, but the tradeoff is often lower peak frequencies. The design here was to ensure fitting into that 75 watt power envelope anyway.

IBM’s previous approach required using a single closed-loop IIR controller that stalled AI cores when the power budget was nearly exhausted, similar to a time-muxing or duty cycle. This method works, but it is conservative by design, and means that throttling is based on a single set point at a single time constant.

Spyre replaces that completely with a dual-loop system: a fast inner loop handles peak-current spikes on short timescales, and a slower, software-controlled outer loop adjusts the average-current target based on actual workload behaviour in real time. The two loops operate with different time constants and setpoints, allowing the system to use the available power headroom safely during short bursts without violating average power limits over longer power windows.

The result, based on IBM’s ISSCC 2026 data, is a 25% higher inference throughput compared with using a single-loop controller under the same power budget. For encoder models, the boost ranges from 7 to 32% depending on sequence length and configuration. That isn’t just a trivial gain for the sake of it, and it also requires no changes to the silicon whatsoever.

Before taping out, IBM also made several design decisions to reduce the overall baseline power. The AI core array itself runs at 0.55V while the SRAM and third-party IP blocks run at 0.75V. IBM also made the counterintuitive choice of the larger 7T standard cell library over the denser 6T option, because testing showed that the 6T library actually drew more power at 0.55V due to the need for additional buffers. A total reduction of 9% in synthesis frequency target before tape-out managed to cut power by 7.5%, with re-synthesis adding further power and area savings of around 8% and 6% respectively.

Scaling Beyond One Card

A single Spyre card handles encoder workloads comfortably within its memory budget, and while typically large generative AI models are a different proposition altogether, many simply do not fit in 128 GB before batching is even considered. IBM addresses this through RDMA-based multi-card scaling, in which multiple cards communicate via a PCIe switch, enabling direct card-to-card RDMA transfers at 64 GB/s with CRC protection, bypassing the host CPU entirely.

IBM’s published data for its optimized Granite-3.3-8B model show near-linear scaling with four Spyre cards, with continued gains extending to eight. As cards are added, each one handles a smaller compute chunk, the total memory bandwidth aggregates, and both time to first token and inter-token latency improve in parallel.

A fully loaded IBM z17 supports up to 48 Spyre cards per tray, 192 cards per system. That puts 6.1 TB of accelerator memory inside the mainframe’s security boundary. IBM Power11 supports up to 16 cards per system. No comparable GPU server configuration delivers 6 TB of accelerator memory within a single system at enterprise-grade reliability and security.

What Spyre Is and What It Is Not

While NVIDIA’s high-end hardware runs anywhere from 700 W up to 1200 W in the most dense systems. In the future, that is set to scale up multiple kilowatts per chip. Comparing Spyre to an H100 for example on TOPS isn’t really any kind of comparison that anyone should be making. They are built for completely different environments with completely different constraints.

The relevant comparison is in single-slot enterprise inference cards, where power efficiency and memory capacity per watt matter more than raw throughput. In that space, 128 GB of LPDDR5 at 204 GB/s within a 75 W budget is a strong position. NVIDIA has its options, but IBM also sits in a busy market with a number of inference focused cards from 75 W up to 300 W from startups such as Tensordyne, Tenstorrent, d-Matrix, Rebellions, Furiosa, Qualcomm, Taalas, Positron AI, etc.

One of the key aspects today is the disaggregation of transformer workloads between prefill (compute bound) and decode (memory bandwidth bound). IBM doesn’t particularly isolate Spyre into one of those buckets, showcasing that for its workload portfolio, it can be a one-card solution. As workload disaggregation understanding improves, we might expect to see this to change in the future.

What We Do Know About the IBM Spyre Ecosystem

When then chip was still in the transition from research chip into enterprise product, IBM held presentations about the future of the product line, some of which would be leveraging IBM’s expertise in manufacturing, manufacturing, and system scale.

This is IBM’s Mukesh Khare in 2022, who we’ve interviewed a number of times, showcasing the AIU before it became Spyre. The next year, he discussed that future generations would look to leverage higher speed memory types, as well as packaging chiplets together into one SIP. It’s unclear if the goal is still a PCIe card or if it will move to an OAM form factor that high-powered AI chips currently use. Recently IBM announced a partnership enabling Arm-processing modes to its CPUs, and we have to assume that access to Spyre might become part of that as well.

IBM Spyre SoC: Concluding Thoughts

The primary story for Spyre is very solid, with 8 years of development, 5 generations of test chips, 3 process nodes, and a production design backed by years of real-world hardware data before it shipped out to customers commercially. The dual-loop power management system is a genuine engineering contribution, and the memory capacity advantage over competing single-slot options is a real and meaningful design choice for the workloads it is targeting. Enabling cross-platform deployment across its IBM Z and Power is a sensible strategy through using PCIe looks to have been executed pretty cleanly. PCIe should also mean these cards could work under x86 and Arm, although IBM hasn’t disclosed this use case yet.

What cannot be evaluated yet about Spyre however is whether or not enterprises running IBM Z and Power platforms will adopt the levels of generative AI at the scale where Spyre’s specific advantages become the deciding factor in this form factor. IBM often keeps the consulting business hardware costs close to its chest, so we might never find out!

Update from Ian:

We actually spoke with IBM back in 2024 about its Spyre card, back then called the AIU. You can see all this content on YouTube:

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More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

This year at CadenceLIVE, its annual event, the company is emphasising the fact. A couple of months ago the company announced ChipStack, its new orchestration layer for its tooling. At the top, a head agent has access to five super agents, each in control of different parts of the chip design workflow. Each of these super agents has the ability to access other micromodels and learn skills over time to help architects and chip designers improve and iterate on their design, in both the analog and digital domains. It’s this approach to chip design that Cadence believes will supercharge the current run of chip design, leveraging better PPA and time to market.

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That is the backdrop for this discussion with Cadence CEO Anirudh Devgan, which focused on how the company sees agentic design evolving, how it expects to price that transition, why it believes orchestration should sit with the tool vendor rather than the customer or a general purpose model provider, and where all of this may lead next across physical AI, scientific discovery, robotics, and the broader system design stack.

The following was edited for clarity.

Anshel Sag, Moorhead Insights: How does the pricing of what you are doing change with an agentic approach compared to EDA tools using per core or per seat licensing? How does that evolve?

Anirudh Devgan: Three things are going to happen. The agents are going to be used as tools, [sold as a license] so license demand should go up. The license numbers are already increasing somewhat, so that still supports the traditional business model.

Then there are two new layers. At the top layer, it becomes more like LLM economics, with consumption based pricing. We have already tried that with new customers, and they are willing to do it. The agentic layer is also doing work that EDA never really did before, like writing RTL or generating verification code. This is augmenting the human capability.

So there are really two new models there. One is that we charge for the agent, based roughly on the amount of work one human might do. The other is the consumption model. If an agent can do ten blocks instead of one, then consumption rises accordingly.

So price per agent is new, consumption is new, and at the same time there is more demand for the traditional baseline licenses. When I talk to big CEOs and major customers, they are fine with that as long as there is clear value. They would rather pay for that than hire more people. That is important.

Leonard Lee, Next Curve: In the horizons you laid out, science AI appears later, but in some ways that is already happening. Traditionally we have seen scientific discovery tied to supercomputing, and now quantum is also often discussed in that context. Why place that later than the present?

Anirudh Devgan: All of these things are happening already. Some people do talk about them that way. For me, it is more a question of critical mass. It is like robotics.

These things are not all happening at the same speed, and drug discovery is not moving at the same pace as robotics. We are already working with all the big pharma companies, probably the top fifteen or twenty. So it is happening. But it still needs to reach escape velocity. LLMs have already reached escape velocity. Robotics is getting there. Science will take longer. Once it reaches critical mass, it could be even bigger than robotics or physical AI. It could become a multi trillion dollar opportunity.

For me, 2026 is really the start of physical AI. The biggest invention of the last few years is self driving. Drug discovery and medicine could end up being bigger [than self driving], but that depends on how quickly they reach escape velocity.

It is not just AI, but AI plus custom hardware. The biggest breakthrough is self driving, whether you look at Waymo or Tesla. In five years, the number of people driving cars could be much lower than today. And if you can self drive cars, then eventually you can self drive ships, drones, and defence systems. Drones will happen. Industrial robots will probably come first.

So physical AI has already started on that escape velocity curve. It may not be visible to everyone yet, but it is getting there. In pharma, progress may be more drug specific and more dependent on the problem. We can already do candidate selection, but a true breakthrough in drugs or materials science will take more time. If you say everything is happening at once, no one believes it. It is really a matter of timing.

Steven Nellis, Reuters: Why is orchestration such a computationally complex problem, and what is your differentiation versus companies building their own agents?

Stephen: Jensen may want to use yours, but general purpose agents from others will also exist. If the orchestration layer is really coordinating a set of point agents that know how to use tools, why is that a problem that naturally sits in your wheelhouse? Today that orchestration is often just people coordinating other people and meetings. I am not sure what your advantage is compared to others coming from general computational software.

Anirudh Devgan: There are really three types of entities that could do the orchestration at the top. It could be us. It could be the customer, and they are doing some of that already. Or it could be a regular LLM provider.

The reason we think we will be best is straightforward. First, we can call the tools in a very granular way through our APIs. Customers like NVIDIA and others will write their own agents, and LLM companies will also interact with tools, but usually at a much more basic level. We can look inside the engines. We know the software details at a much deeper level, and that is a fundamental advantage.

Second, we have the right mental model. We understand the chip stack and the domain specific details. Customers will absolutely write their own agents. They already are. Agentic flow is really a better orchestration of the design flow. The implementation tools already have specific interfaces, and every company has its own way of calling our tools. They will still do that, but now they can do it with agents.

So yes, there will be lots of agents. Customers will have their own. But the big agents, the broad orchestration agents, will be done with us. When we show our customers our stack, they generally do not want to recreate the whole big function themselves. They may want domain specific functions, but not the full thing. That is what I see happening. We want to make sure customers can use our agents or call their own agents if they need to. But the main work will be done in our super agent. We have shown this to many customers now, and it is a lot of work to build.

As for the LLM companies, they need tools and domain knowledge. They will keep improving the models, and they may have some domain specific areas like cybersecurity, but they do not have enough data in this domain. In all my interactions, whether with Charlie (Broadcom) or with Jensen (NVIDIA), they already have enough to work on. They have very big problems in physical design, analog, digital, and so on. There is no real need for them to deal with this entire layer themselves. For some specific chips, yes, they might have their own agents, but we will have ours too.

Steven Nellis, Reuters: What if a customer wants direct access to those APIs?

Anirudh Devgan: You need a full R&D team to do that. Even with the current interfaces, we have access at a deeper level. You need to know the history and the algorithms. The big companies generally do not want to work at that layer.

We have shown this to many companies. The real question is why EDA companies can do this now, after more than thirty years of workflows and tools. We always wanted to automate more, but before there was no algorithmic way to combine knowledge and workflow automation. Now there is.

I am showing real demos. We want agents and models with skills. The hardware matters too. We have the data, the knowledge, and the hooks that are specific to this domain.

Nina Turner, IDC: When you talk about orchestration inside the flow, are you talking about functions, overlays, handoffs? And if that happens, is it only within Cadence tools? Some designs use tools from multiple companies for different functions. How would that work?

Anirudh Devgan: Our overall flow, what we call AgentStack, is much bigger than just RTL. It has a large backend component, and our IP team is very excited about it too. IP is not as profitable as EDA, but with this kind of tooling we can operate like a team that is twice the size. It becomes an environment for our mixed signal IP as well. That is why I emphasise the stack.

Customers can write their own agents, or call it from other models if they want to, and they can write their own skills too. When it comes to mixing tools, we will have to see. They could call another agent if they wanted. But our goal is to make sure we have the best tools and the best agents.

As workflows become tighter, there will be more verticalization. In the old days, companies might have had a zig zag flow between different vendors. Now we are moving toward more vertical flows. Part of that is because advanced nodes are much more complicated, but part of it is also because AI makes tighter integration more valuable.

What is likely to happen is still some splitting of designs between different flows at a high level. But our goal is to have the best PPA, not just the best agentic layer, but also the best base tools. We want to be the premium option. The more complexity there is, the more there is a need for verticalization.

Anshel Sag: Do you have plans or concepts for a major agent to orchestrate over everything?

Anirudh Devgan: That is our AgentStack. It is the head agent for the super agents. It is a hierarchy of agents. We have five super agents under AgentStack, and then twenty to thirty agents under those, because each tool will ultimately have an agentic interface. But AgentStack is the head agent.

Chris Rommel, VDC Strategy: For twenty years we have been talking about EDA leading into system of systems design. Beyond the investments you are making, what are the things that can help Cadence become that head agent versus other tools, not just the other EDA players but everyone else trying to steer workflow across domains?

Anirudh Devgan: In the end, it comes down to who has the best solution. We are very confident in the super agents. We need a head agent to bring them all together, and we need that to be consistent. But ultimately the real differentiator is the quality and scale of the super agents. They are as complex as the base EDA tools themselves.

Another thing that matters is our customer base. 70 to 80 of our biggest customers represent most of our revenue. This is very different from a SaaS business. And something that is often not appreciated is that every week we have multiple R&D meetings with those companies.

In engineering software, they tell us every week what they want, and they want these super agents. For them, it is a waste of time to write those from scratch. If we do a good job, with the right team and the right technology, there is no reason for them not to use it. Our customers want us to build it.

For others, it becomes a mathematical problem of combining the layers. For example, all the LLM companies talk to us anyway. The opportunity is to substitute manual work with automation. We showed our analog stack to customers and demonstrated how we can automate what they are doing. In the end, the best product wins.

Fudo Abazovic, ACAnalysis: Can you talk about digital twin, and markets beyond AI datacenters?

Anirudh Devgan: We are seeing good results there already with the hyperscalers. The other major area is robotics. One reason we made acquisitions is because if robotics becomes a $250B billion dollar market, then the sim to real gap has to get much smaller.

Atoms had the most accurate approach. If you look at environments like Isaac from NVIDIA or MuJoCo from Google, they keep improving the physics, but it is still game physics. It is good for movement, but not always for detailed interactions. The most accurate multi body dynamics came from Atoms (a company Cadence acquired). The issue used to be speed, but now we can get it close to real-time.

When I talk to robotics companies, one of their biggest challenges is what happens in that last millimetre, when something grips or deforms an object. That is where digital twins can play a very important role. That is the first focus.

Another area is CFD for drones. We did a project with Boeing that showed only about twenty percent of the desired simulation was being done, simply because the simulations take too long. Now, with our software and GPUs, we can accelerate part of that. So the sim to real gap in physical AI, along with CFD and aerospace, is a very important opportunity.

Nitin Dahad, EE Times: All the EDA companies have made investments to broaden access beyond traditional chip design firms. How accessible is this beyond the seventy to eighty companies you already work with, especially with respect to agents and the broader ecosystem? What about emerging companies that want to do chip design but do not yet know how, or do not have the resources?

Anirudh Devgan: You can blame me for the move into system space back in 2018. But this is 2026, and a lot has changed. We wanted to get into systems and diversify, and there is synergy there. I still like SDA (System Design Automation), but the value of EDA is much higher. We need to focus on the core business, which is the agentic flow.

SDA is good, but it is only part of the picture. 3DIC is interesting. Robotics is interesting. We now have more than a billion dollars of SDA business and it is growing. But the opportunity in EDA is re emerging in a major way.

If we can automate more of EDA with agentic workflows, then the larger system companies can do more silicon, extending beyond the datacenter into areas like robotics. So in agentic, the opportunity is huge within the core business. More system companies will do silicon, and there will be more automation from our side.

We still invest proportionally in those adjacent areas so we do not miss the opportunity, but EDA remains our core business. About eighty percent of the action is still happening in chip design. Customers can also do much more. We may only be one hundred times better than ten years ago, but there is still room to do ten times more than that. For example, automotive companies want to design more chips.

Leonard Lee: Agentic is a big topic this year. Where are your customers on the adoption curve? Is it early?

Anirudh Devgan: It is still early. A lot of them are writing small agents today. It depends on the company. Really, only in the last six months has the ramp increased significantly for us and for them.

That is why we acquired ChipStack. We launched in February, and now we are having much deeper conversations with customers. But it is moving very fast. The value is being realised because of the automation.

So yes, it is still early, but there is enormous interest. Rather than build everything themselves, they are asking us to do it, and we are ahead. It is early days, but they want these capabilities inside the environment.

For example, with VeraStack, you can call it from Claude, but because we have integrated it into Virtuoso with the key APIs, customers prefer to do it with us.

If you want, I can now do the next pass properly in your usual transcript house style, meaning tighter intro, lighter cleanup of the answers, and with the speaker tags formatted exactly the way you normally run them.

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

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That is why Synopsys matters. For years, it has sat near the center of modern chip design, providing not just EDA tools but also the IP, signoff, and increasingly the physics aware co-design infrastructure needed to bring advanced silicon to market. A few years ago, I interviewed former Synopsys CEO Aart de Geus about where EDA was going and how the industry was changing.

Coming back now to speak with new CEO Sassine Ghazi, the conversation feels both familiar and very different. Familiar, because the core challenge remains helping customers build ever more ambitious silicon. Different, because the problem has expanded. The old model of simply riding Moore’s Law forward is no longer enough. Today, customers are dealing with one year design rhythms, disaggregated architectures, 3D stacking, thermal constraints, and the need to bring manufacturing physics much earlier into the design flow.

I caught up with Sassine Ghazi just after he came off stage at Synopsys Converge, the company’s annual event, where much of that future was on display. In this interview, we talk about how Synopsys sees the chiplet era, why Sassine says the company did not just embrace that shift but helped enable it, what the Ansys acquisition was really about, and how the industry is moving from simply designing chips to co designing chips, packages, thermals, materials, and software behavior all at once. We also discuss Synopsys’ work with Rapidus as it tries to stand up a new leading edge foundry, and where agentic AI may actually fit into the chip design workflow, beyond the marketing language and into something that can deliver real engineering value.

The following is a transcription of the above video. It has been edited for clarity.

Ian Cutress: Given the nature of chip design, it’s accelerating; we’re all seeing it. Companies are now not only producing more products but also in greater volume. How is the Synopsys business model changing?

Sassine Ghazi: The complexity and pace, that exponential, is getting steeper and steeper.

If we go back 15 to 20 years ago, we followed Moore’s Law - our customers owned their architecture, we provided the software to enable and implement the chip, and then the customer themselves, with the foundry partner of their choice, would manufacture it.

About 10 years ago, the complexity between design and manufacturing became more intertwined. We played a role in optimizing between design and technology. You look at the chips today with the requirements of AI, and the architecture flavors are rapidly evolving. The complexity of getting the power and performance needed is no longer following Moore’s Law, so there are different approaches, advanced packaging, multi-die, etc. You need a very sophisticated EDA and a tremendous number of IPs to connect these chips together. We’re in a unique position because we lead in EDA technology and have the broadest IP portfolio, and our customers have been spending a higher percentage of their R&D on that automation.

Ian Cutress: So time to market is becoming more critical for your customers?

Sassine Ghazi: Absolutely, because it used to be 18 to 24 months to design a chip. Now, customers are working to a one-year rhythm to deliver new silicon, which just means more pressure on everything they do, be it the software we’re providing, or new techniques, to shrink design time.

Ian Cutress: One of the first companies to integrate chiplets through heterogeneous integration had a difficult time doing so because there were very few tools available. These are the sort of tools your company produces. How have you embraced the chiplet era?

Sassine Ghazi: We didn’t just embrace it, we enabled it. Because if you think back to architecture, as you disaggregate from a monolithic to a chiplet, you don’t do this manually. Which part of the chip goes on which technology node? Where do you put it in the stack if you’re stacking in 3D? What is the memory role in it?

We have a technology we call the 3DIC Compiler, where you start from a specification and go architect the advanced package or chiplet, whatever you want to call it, and do the what-if analysis. If I use 5nm for this instead of 3nm, what do I get in terms of power, etc.? Then the connectivity between these chips is a whole new level of complexity; that’s where UCIe was born, with PCIe, HBM, etc., to connect the system together. And it’s a fantastic opportunity, because what we’re seeing now is not only semiconductor companies designing these chips, but hyperscalers themselves moving from general-purpose to ASICs to COT (Customer Owned Tooling).

Ian Cutress: With tools like the 3DIC Compiler - is that something borne out of customer requirements, or did you already have an ongoing internal project to deliver it?

Sassine Ghazi: We see things very early with the customers, and the 3DIC Compiler is a great example. Around 2017, we could see customers looking for different architectures and packaging to achieve better performance and power, rather than relying solely on Moore’s Law. We started exploring and developing the technology back then, before the first adoption came around three to four years later. As that first adoption came in, we discovered a new challenge: physics. Customers exploring manufacturing before going into production found thermal issues, warpage, and die cracking during packaging. Physics needed to be integrated, and that’s where we embarked on truly transforming our company with the acquisition of Ansys.

Ian Cutress: On that front, especially with thermals, I found a bunch of IBM patents on intra-chip cooling from the 90s and 2000s. As we look at multi-stacked chips, the next stage is surely intra-chip cooling, which means you’ll have to model it for your customers.

Sassine Ghazi: Yes, exactly. And beyond modeling, there are certain hot spots on the chip that you don’t want to overdesign for. Do you have visibility into the software that will run on that chip?

So you can design just right, not overdesigning, keeping costs down, but at the same time making sure it’s not heating up when you run a certain corner case.

Ian Cutress: That means if you’ve got a workload that attacks the ALUs or the memory in a certain way, can you design for that workload, but then you might end up with a workload-specific chip?

Sassine Ghazi: Exactly, otherwise, you just overdesign, and when that happens, not only is it expensive and time consuming but the chip is not competitive either because you’re building so much margin between its different functions. What we announced today, our Multiphysics Fusion platform, is about bringing those physics models into the design phase itself, taking into account the IR, the thermal, the electromagnetic, and the mechanical, so you’re co-designing rather than overdesigning. We introduced that concept with the fusion platform. Ten years ago, the challenge was less about physics and more about how do I close the timing on the chip, how do I close the power?

Ian Cutress: Does wafer scale present any additional problems?

Sassine Ghazi: The challenge is more how do we model on the manufacturing side at the device physics level, and then at the packaging level. At the architecture level, if you’re designing it with that architecture, is this the best representation of the physics that you’re going to manufacture with? So in a sense, yes, but from a Synopsys point of view, we look at it as DTCO (Design Technology Co-Optimization). With the various flavors and models of the physics and what our foundry partner is going to be providing as a solution.

Ian Cutress: In terms of EDA and especially IP, getting it to work on a specific process node is a key aspect of the product. But a lot of what you’ve spoken about today, and a lot of what we’ve discussed, is almost process node agnostic. So how much do the foundry players get involved?

Sassine Ghazi: That’s true for IP, in a sense. We have the broadest IP portfolio, but we have to provide it to our customers on the various technology nodes with various foundries, otherwise you’re not the leader in IP. If you say I’m only doing it for that one node with one foundry, then customers will end up building their own IP. So the work we do with multiple foundries requires a lot of close partnership and collaboration, because we’re there at a very early stage of their PDK development, etc. Same on the EDA tool side, when we are designing Fusion Compiler, or for that matter, PrimeTime or RedHawk, etc, you need to know what implementation of materials and physics they’re using, so you’re designing the tool and the algorithm to match it.

Ian Cutress: So we’re even talking about what material they’re using for liners and interconnects within the chip. Because that’s all the physics of how these metals work.

Sassine Ghazi: Our tool implements it because the customer has a requirement. They design it at, and I don’t want to oversimplify what the customer is doing, but you kind of said it. The software we provide, it could be argued, is as complex as what our customers are trying to do. But we are the bridge between that architecture and if you can manufacture it, that’s where the signoff strength comes in.

Ian Cutress: On foundry, Rapidus is the first new leading-edge foundry from a new entrant into the industry, I would argue perhaps the last time that will happen in my lifetime! From your perspective, does working with a new partner on leading-edge IP introduce challenges compared to someone who’s been doing it for 20 years? Can you go into how you’re working with them?

Sassine Ghazi: We have a fantastic relationship with Rapidus. When I talked to our Japanese team, I said Rapidus is a gift for us, especially when it comes to Japan as a starting point. Of course, they’re not going to be a foundry just for Japan; they have an ambition to be a global foundry. The reason I say it’s a gift, from a technology point of view, they have a partnership with IBM on process technology. We have a technology called TCAD (Technology Computer-Aided Design), which models the device and the process technology when the technology is at the R&D level. So before you go anywhere near production volume. We started that engagement at that level. Then, as the technology matures, when you’re doing a test chip, the design representation is a PDK (Process Development Kit), and you start from a 0.1 PDK, then evolve to 0.5, 0.7, etc. So we’ve been working very closely with them on both the technology process level, through EDA and design, and to IP.

Ian Cutress: But does it change because they’re new into the industry? Because what you’ve just described is what you do with every foundry when they have a new node.

Sassine Ghazi: Sure. Other foundries go from node to node to node - there is that incremental and cumulative learning. Here, some of that cumulative learning came from their partnership with IBM. But of course, it takes longer because that is the first node they’re creating. The nodes that follow from Rapidus will be exactly like other foundries. From a Synopsys investment point of view, it’s a higher investment, but that’s where we bring tremendous value to that foundry: our tools have seen everything from planar to FinFET to Gate-All-Around, so we’re not reinventing anything in our product.

Ian Cutress: If I look back to 10 years ago, and we had a discussion then about the next 20 years of EDA, we would have arguably said we expect more of the same with incremental increases. But now we’ve got new degrees of freedom in multiphysics and 3DIC and verification and simulation. The question then becomes, what are the next five years going to look like?

Sassine Ghazi: The reason we shared the framework for agentic AI last year is that there is no question that we see it as a significant opportunity. We introduced reinforcement learning into our product in 2020, with general market availability, and we started investing in it around 2017. Looking back over the last three years, the speed at which models are innovating, the way the orchestration of models is evolving, and the opportunities it’s providing are unbelievable. A big part of our roadmap is looking at the entire chip workflow and asking which parts of it can be assigned to an agent. We call them agent engineers. How much can you have an agent managing an agent, i.e., orchestrating these agents. What we announced earlier today is the first level of multi-agent adaptive dynamic orchestration. These agents are learning as they operate on new data and new requirements, and on how to achieve the final goal and target. The innovation will continue at a very fast pace. The key, which is the layer that we’ve invested in, is to move every part of Synopsys, every product, every solver, to be working with the latest AI technology, like reinforcement learning or other technology that is available.

Ian Cutress: So you’re talking about an agent calling a solver, getting a result, examining the result, and then maybe calling the solver again, iterating and learning?

Sassine Ghazi: Exactly. What we have today are these task agents, or agent engineers, where the human engineer assigns them a task, they go off and come back with an outcome, and then the human engineer makes changes, etc. There’s a cognitive layer, and the orchestration layer can be adaptive; that’s where we have partnerships with Microsoft, NVIDIA, and others. They’re doing a very good job racing ahead with that cognition and orchestration layer. So we’re not trying to reinvent what is already out there, but rather what do we need to do with our core assets, which is the solver, and bring in AI to accelerate.

Ian Cutress: You have to promise me something, because if I were being facetious, I would say that sounds like a middle management pyramid scheme of orchestration. So, as best as you can, please don’t make it that!

Sassine Ghazi: Oh, you’re talking about the agent of agents as the orchestrator?

Ian Cutress: Yeah.

Sassine Ghazi: The knowledge actually doesn’t decrease as you go up the agentic workflow; it’s the opposite. The reason I was very specific in the words we used earlier today, it’s a dynamic adaptive orchestration. That sophistication in technology to optimize. I was talking to a customer before my keynote, and one customer who’s testing these things said it’s impossible for a human to look across that huge space. So that’s not an agent engineer competing with a human, it’s exploring a much larger space and seeing what is possible. So yeah, definitely it’s not a management scheme.

If you want to catch what’s happening at Synopsys Converge, please check out the links below.

• https://www.synopsys.com/converge.html

• https://www.synopsys.com/blogs/chip-design/synopsys-converge-2026-silicon-systems-conference.html

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

Today, Pat is no longer running Intel. Instead, he is operating from Playground Global, where he has shifted to helping identify and shape the next generation of hard technology and hard physics bets. But in many ways, the themes are familiar. He is still thinking about the future of compute, he is still thinking about architectures, manufacturing, software, scaling, and he is still thinking about which new ideas have the technical depth and leadership to matter. In the interview, he describes this stage of life as focusing on things that matter, with people he enjoys, and says Playground gives him a way to stay close to companies he believes could shape the industry.

That broader perspective is what makes this conversation interesting from my point-of-view. This is not just a retrospective on Pat’s past, and it is not just a venture capital conversation either. It is a discussion with someone who has spent decades building and leading in classical compute, and who is now looking outward at AI accelerators, dataflow systems, resilient networking, quantum computing, and the growing pressure to make inference dramatically more efficient. Pat argues with me that inference still needs to improve by orders of magnitude, that the future is fundamentally heterogeneous, and that the next real breakthroughs may come from combining what he calls a “trinity of computing”: classical, AI, and quantum systems. Whether you agree with all of that or not, it is a view worth hearing from someone with Pat’s knowledge and experience.

In this interview, we talk about what changes when a former Intel CEO starts evaluating startups instead of product roadmaps, how he thinks about proof, market fit, and leadership teams, why he believes the industry is still early in the real buildout of agentic and scientific AI workloads, and where he sees the next pressure points in compute, from precision and resilience to optical links, dataflow machines, and the search for architectures that move beyond a purely von Neumann view of the world.

The following is a transcript of the video interview embedded above. Phrases have been adjusted slightly to improve readability.

Ian Cutress: We’re here at Playground Global, which is Pat’s new home. How’s it going?

Pat Gelsinger: I’ve just turned 65, and I'd say at this phase of my career, I want to do things that matter. If they succeed, it makes a difference with people I enjoy. Playground is a place I can do that.

I have about 10 companies that I’m deeply involved in right now. I’m on the board of most of those, and I think some of these are going to be industry-shaping companies. If I get to help build great companies with great leadership teams at this phase of my career, this is good. And so far this year, [although] I’m a rookie in venture capital, the team has have embraced me and we’re making a difference.

Ian Cutress: Did you ever see yourself eventually migrating into this sort of role? It’s a bit hard to go from a sustained big company sort of position into venture capital.

Pat Gelsinger: Remember, I was in the industry for 45 years! When I left Intel the first time, to EMC, literally I retired one night, and started the next morning. When I went from EMC to VMware, I literally did both jobs for two weeks. When I left VMware to come back to Intel, I did both jobs for four weeks.

It has been 45 incredible years, so after leaving Intel, my wife walks into my study literally the next day after the announcement of leaving Intel and she said, “you’re not done yet”. I think that means “don’t be home too much”! I have a little bit too much energy I guess!

That began a 100-day journey for me of figuring it out, of what do I want to do next? And I interviewed a lot of venture firms, private equity firms, a bunch of CEO roles, and government roles. It was when the Administration was coming in. University roles too, and at the end of that, I decided I wanted to make a difference, and Playground came at the top of that list.

Then there’s also my Gloo company, the faith technology company. So I’m splitting my time between the two of those. I want to make a difference eternally and make a difference in the future of science, and bring those two together. That’s a pretty good position in life.

Ian Cutress: I can’t imagine how many people came out of the woodwork to offer you advice on the next stage?

Pat Gelsinger: Lots. Of course I wanted their advice too. I had what felt like 100 meetings in a 100 days to figure out what was next - and here we are a year later and it’s going pretty well. A lot of it is in semiconductors, but you know I’m doing Alva Energy, nuclear upgrading. I didn’t know anything about nuclear energy. Now I’m doing that too.

I am learning a lot too. I’m doing superconducting, Josephson junctions and such. It’s sort of in the computing ecosystem, but wow, those are really different looking transistors from what we thought - to now worrying about cryogenics. It’s stretching my mind into quantum computing - and for a digital boolean guy for my entire life, it’s like you’ve got to turn your brain to a 90 degree angle to think about qubits and how they’re functioning and tangled and how you use them to compute. So it’s a lot of learning for me personally. I say the only disappointment I have at this phase of my career is I’m not 35 years younger! This is the greatest time to be a technologist in human history.

Ian Cutress: So in my mind I’m seeing you at a desk pouring through papers of potential startups trying to find the one that’s got something a bit unique.

Pat Gelsinger: I’m reading a lot, so lots of papers and that’s part of it. A lot of that work gets done by our associates, so I’m like that one sounds pretty interesting and they’ll seek my advice on how it would fit into the industry. They’ll go do work, we’ll meet. I like reading but even more so, I like interacting. To me, if I could read for ten hours or meet with the company for one hour, that one hour is more valuable.

Ian Cutress: So you’d rather have the college lecture?

Pat Gelsinger: Well, it’s not the college lecture. It’s the questioning, the interaction. I want a few smart people at the table. I want to ask questions and I want to hear their questions, how they respond, and that’s my best learning modality. But yeah, I mean, my brain is being stretched in so many dimensions. I’m learning about bioengineering, how semiconductors are being applied to bioscience as well.

It’s what I call the trinity of computing - the fusion of classical, AI and quantum effects coming together. I think that will be literally the problems that we will now be able to compute. Almost everything that we’ve been able to express mathematically will now become computable.

I mean you just have this powerful new tool coming over the horizon with quantum computing where many of those quadratic functions that were uncomputable before. Now they’re sort of like, yeah great let’s go attack those portions of the problem as well.

Ian Cutress: So how do you marry the fact that you’re not completely green and brand new but these are new degrees of freedom for you to explore, then also evaluating whether a startup is actually worth the investment right? There is something to be said for the person who spent 40 years in a space and their add-in to that discussion!

Pat Gelsinger: You sort of come down to three questions. One is if we can make the technology work, is there real proof - we like to do hard tech things. So there really is this question: Does the tech work? Then you’re sort of saying, okay, how does it get to market, how do we bring it to an at-scale deployment? Then the third question is if we have the team to do it.

With the leadership team, we have brilliant technologists asking the hard questions: what are the milestones and the way to show that we get there, the market insertion. By the way, that’s part of my unique value. I’m able to call up CEOs throughout the industry and say, hey, don’t let this one get stuck down here as some entry-level person as you evaluate it - this one matters. Let’s work together on how we differentiate your offerings, your GPUs, your networking components, your business using these. That connectivity helps quite a lot with number two, driving that business development and accelerating it into the marketplace.

And then, with 45 years of major leadership roles, my job is to shape leaders into great CEOs, great CXO teams. I give them some pretty tough feedback sometimes! Some of them are great leaders but can’t present slides to save their life. Okay, we’re going to make you at least a mediocre presenter, you’re going to be able to do that. In other cases, they’re great presenters but not great leaders. How do we build a leadership team around you? In other cases, we’ve got to show them how to make a sale. There are all these things associated with building a great company. Since I’ve been in these big leadership roles, I really enjoy bringing that to the CEOs. But the hardest thing, Ian, I don’t have my hands on the wheel. Every once in a while it’s sort of like [mimes grasps the wheel]!

Ian Cutress: You can lead a horse to water, right?

Pat Gelsinger: Yeah, for some of those! But it (the new job) also does give me a lot more flexibility as well. “So, tell me how you solve this one? On my desk by Monday morning because I’m taking the weekend and taking my grandkids skiing.”

Ian Cutress: I’ve been seeing some of the magic you guys have done with our good friend Mark Wade over at Ayar Labs. They just did their Series E. Mightily impressive, and they seem to have funding from everyone now.

Pat Gelsinger: Well, I’ll say there’s this characteristic where you get a term sheet, somebody ready to lead the round, price the round, and then people are ready to jump in. And there’s this sort of interesting thing - what’s going to cause that dam to break?

Ian Cutress: Did you mean that in the sense of people don’t want to fund, or it just may end up being oversubscribed?

Pat Gelsinger: Everybody is sort of around the table, but who’s going to put the lead term sheet down for this round? Who’s going to price the round? Who’s going to say I’m going to put the biggest check into this round? And as soon as it’s them, or maybe it’s two who are sort of co-leading the round, then others are ready to come into it. The round is going to get formed. We’re going to see it now, we want to be part of that as well.

That was very much the case with Mark and the Series E. Once we had that lead term sheet, it sort of broke the dike a bit, then the energy unleashed of many other people wanting to come into the round, and quite a few strategics as well. So to me, as I’m learning the venture game, if we could call it that, having that network of people that I am confident are going to be leading with me to form rounds in timely fashions, because if it takes us three months to form a round, that’s three months later in the market as well. And I don’t want to let some of the hottest companies languish in competitiveness by not moving them forward effectively as well.

Ian Cutress: Speaking to a few people in the last couple of months, since Nvidia’s acquisition of Groq, a lot of people who are raising have suddenly found it’s getting easier in 2026. Are you finding similar?

Pat Gelsinger: Clearly that was catalytic! Nvidia is not going to acquire ten companies in that space - they were clearly deficient in having optimized inference, and as I said at GTC last year in the pre-show, we need to make inferencing 10,000 times better. Not 10x, not 100x, 10,000 times.

Ian Cutress: That’s a great headline! 10000x vs 10x. But as always, the question is how?

Pat Gelsinger: When you think about it, it’s replacing search. Now with OpenClaw, something none of us quite predicted, even though everybody was predicting agentic. It’s just demonstrating that okay, we’ve got to make inferencing a lot better. My “10,000x” was sort of a number that I pulled out based on some math of where search was in terms of energy, compute, cost. But as proud as NVIDIA are, and should be around the incredible progression of the GPU, it got them to say the GPU is great for training, it’s great for some of the waterfall training into inferencing, but it’s not an optimized inference chip. And that led them to (acquire) Groq. But now there’s 20 companies pursuing that assignment, asking how can we be 10x better or 100x better than where Nvidia just described the LPU with the Groq design.

Ian Cutress: I had to tell you, but I’m tracking 150 these days [laughs]. It’s anything from pre-seed, all the way up to IPO. Avariety of SRAM focus based, dataflow, people talking about HBM5 and high bandwidth flash.

Pat Gelsinger: I’ve got to see your list!

Ian Cutress: When I look at the Playground companies that put you in their press releases, it seems like a lot of bets you’re making are non-von Neumann these days. Take Snowcap for example, an absolute zero type of computing. Is that where you see the future going, or is this just a “we have to optimize for every workload” sort of play?

Pat Gelsinger: Part of that is the language I’ve used, I’ve called the trinity of computing. We’ve always believed in accelerators. I’ve always believed in accelerators - whether they were SIMD accelerators, SIMT accelerators, MIMD, these other forms of how you attack those workloads. To me, the architecture in that sense, trying to fit the world through a von Neumann lens, means that all workloads look von Neumann.

Ian Cutress: A case of ‘Is the workload defined in the architecture, or is the architecture defined in the workload?’

Pat Gelsinger: In this sense, what we’re now seeing, and I think clearly the surge in AI has said: “hey, different architectures enable different workloads to emerge at scale.” That’s what’s made this period exciting, that all of a sudden those data-centric workloads, with matrix functions against them, are able to do really interesting things. But it’s the workload that matters.

I was saying that before even Jensen was saying that, in some of our debates. So it’s the workload that matters. It’s about which workload is interesting, solving unique and wonderful problems, and then what’s the best architecture to run it on. There’s nothing that you saw yesterday at GTC that can’t run on the CPU, right? That’s the beauty of von Neumann type machines.

Ian Cutress: Can you run Jensen on a CPU? Maybe he’s got a little bit of magic there, but I know what you mean.

Pat Gelsinger: It may not run efficiently, it may take a long time. As we said, there’s algorithms that only can run on a quantum machine. But actually no, I can run them on an AI or classical machine, it’s just they just take a billion years and run out of memory.

I can’t get there from here using that computing architecture. So I do think in that sense we’re going to see this multiplicity, or heterogeneity, of what the compute architectures are, and most of the interesting problems will combine them. Yesterday, Jensen announced a CPU. What a backward thing for him to do! Why are we going back to the CPU?

Ian Cutress: It was funny, because at the beginning of the presentation, I’m not sure if you caught it, he said the CPU is old. It’s the legacy. And then, as you’re right, he then announced a CPU.

Pat Gelsinger: Of course I noticed that! I’m a CPU guy, of course I notice it! So first we’re going to spend half the keynote throwing it under the bus, we don’t need it anymore. Then we’re going to announce that we now have the best one because we need it.

So which is it? Well, the answer is the workloads need both.

There are things that run like crap on a GPU. If I have control flow related functions, they’re terrible on a GPU. Your basic if-then-else is a terrible thing to do on a long pipeline GPU. It may be able to run six different dimensions of parallelism, but if-then-else is not a parallel function. So in that sense I really do see it as a heterogeneous view, and that’s why I call it the trinity of computing. Classical, that’s going to be control flow, tool based, analytics based, operating systems, all of those things, more on the CPU. Then I’m going to have this raft of things that are data-centric and algorithmic that are going to be great on the AI. And then I’m going to have these things that only work because of a quantum machine, being able to apply entangled Qubits against those problems. With that, now we can open up a whole lot of workloads that are not computable today.

Ian Cutress: I know people are going to be shouting at the camera because we discussed this back in the day, and your good friend Greg Lavender was on top of this. It’s the software strategy. You can’t have a heterogeneous installation without having the software that attacks it. I’ve always been a vocal critic of the write-once and compile to target, because it’s never as efficient as you need it. We know working with hyperscalers, they’re going to extract every percentage point of power and efficiency out of code. And you can’t do that at a high level where you might have this heterogeneous ecosystem.

So… it sounds blasé to ask, but what can we do here? We’ve had standards in machine learning, for example on WindowsML, and Intel tried to do it with OneAPI and everything else, but there just doesn’t seem to be any consolidation right now like we’ve had in GPUs.

Pat Gelsinger: Yeah, I do think we sort of abstract, abstract, abstract. Then all of a sudden we need to collapse. I think everybody knows, a little bit over a year ago, was the DeepSeek moment. Well, what did they do? I’ll say they collapsed. They went to really understanding what the machine was doing, getting very targeted on how to use the machines to be much more efficient.

What does an engineer do? They produce great results in the constraints that they have. To me that was part of what made DeepSeek such a defining moment, because they sort of tunneled through the stack, said we really know what’s going on in hardware, we’re going to align our algorithmic functions against what hardware we have available and is capable. I think we’re going to see some of that happening again.

I also think one of our portfolio companies, NextSilicon, building a programmable dataflow machine, is saying “hey, this has all gotten too complicated.” We have to create an abstraction sitting beneath a more programmable hardware embodiment, that is able to statically and dynamically reconfigure itself both in network topology and in compute resource to the most efficient way of the current running workload.

As we’ve all seen in AI workloads, the characteristics of the workload change dramatically. Am I in the prefill phase? As you go through the different phases of computation, big GPUs are turning on and then they’re turning off and power rails are bouncing across the scale, networks are being overloaded and then they’re fallow. So for that I think there has to be this layer of programmability, and that’s part of the reason we’re quite excited about NextSilicon.

But clearly we have DRAM shortages today. Imagine that, four years of great DRAM business, this has never happened in the industry’s history, right? Now you have extraordinary logic and DRAM demand. That never happens in the industry

Ian Cutress: Everybody says we are so used to these bubbles in these commodity markets. And the question I get asked a lot by investors, and I’m sure you do, is when is it going to end?

I’m not sure about you, but I struggle to predict that end because realistically, the only way it’s going to end from my perspective, is if somehow the bottom comes out of the market.

Pat Gelsinger: Well, you know to some degree, the ideal gas law, Jevon’s paradox, whichever way you view it, we’re in a Promethean period of compute expansion. In this sense, when I think OpenClaw clearly has been sort of that next accelerant that all of a sudden, how many tokens per day are you going to use as an engineer. Because, I’m going to spend $100,000 on tokens and I’m going to give you a $200,000 salary. At what point does that become balanced?

Ian Cutress: That’s the argument I’ve made. It’s how much do you want to put into an engineer?

Pat Gelsinger: You know there doesn’t seem to be any end in that value proposition right now. Now obviously as I said we have to make inference 10,000 times better. I do think some of these compute memory architectures are going to have meaningful breakthroughs, that are going to make inferencing dramatically cheaper and not just 10x like we saw from Groq yesterday but 1000x or 10,000x better.

Ian Cutress: Did you see the Taalas announcement earlier in the year?

Pat Gelsinger: No, I didn’t follow that one.

Ian Cutress: So they’re doing what looks like a structured ASIC design. So you bake in the communication metal layers, your model. And they’re seeing 10,000-14,000 tokens per second. Pure ASIC style, traditional ASIC by definition. I’m not sure how you feel about people calling things GPUs versus ASICs, being the traditionalist you are.

Pat Gelsinger: You know, tomatoe tomato right?

Ian Cutress: But investors sometimes don’t realize!

Pat Gelsinger: Yeah, but at the end of the day, market acceptance will be based on tokens per second, tokens per second per watt, aggregate throughput capabilities, latency. It will deduce to real engineering measurable results over time.

Ian Cutress: So my argument against that has always been it doesn’t matter how many tokens you produce if your tokens are useless. It’s about the value of a token. I’m sure you’re seeing the same thing I am - the biggest workload that has value in the token for the output is code - people are willing to pay if you accelerate your engineer. Or I often cite IBM because they have a consultancy business where they generate tokens for their clients and they can upsell and the client just sees you know the reduction in cost. Is there anything we can do you know to stop talking about just garbage tokens?

Pat Gelsinger: Let me disagree with you a little bit. I’m now starting to see very meaningful agentic business process workflows. Where people are turning, nominally, low-end white collar business process flows into highly agentic workflows. Where I truly am putting agents to solve things, for me, that make me more productive, more scalable as well. By the way, that’s sort of what led to the whole SaaS implosion.

As people started to see, “oh, what’s going to happen to my Salesforce, my Oracle” all of those start changing as well. And those are very real. I think that probably becomes the AI pathway into most enterprise workloads as well - once we solve security problems and people get comfortable with where they’re running, whether that’s on prem or in the cloud, or what the security model is, I think that’s powerful.

I do think there’s always going to be a little bit of “my token is different than your token!”, so there’s going to be a question of what “really is the token?” But good benchmarking is going to help us sort that out over time. I’ve done more benchmarks in my career than most humans ever should consider. There’s that phrase, ‘there are lies, lies, and benchmarks’, but you’re still always seeking the best metrics that allows us to deduce differences in hardware. That’s going to get harder as we’ve already talked about with regard to heterogeneous architectures as well. The role of good benchmarking is going to get more important in this next phase.

By the way, it’s going to be critical because people are going to be making billions or tens of billions of dollars of capital decisions based on that work. So it’s going to get more, not less important, because otherwise I’m going to build data centers that produce crappy tokens.

Ian Cutress: I think we started calling it “benchmarketing”. Well, depends on the graph you get from the vendor!

Pat Gelsinger: Remember my code is in the SPEC benchmark, right? One of the most venerable benchmarks of all time. You know, my code is still in there.

Ian Cutress: In 2006 or 2017?

Pat Gelsinger: Yes, all, from the very earliest days of SPECint, my code was there.

Ian Cutress: So which test, which subtest?

Pat Gelsinger: Well if you go into the SPEC benchmark if you look, the espresso flow - that was mine, associated with it, we had the compiler flow - that was my code that we were using in the compiler when we initially did it. I think I have a third one in there as well.

Ian Cutress: Would you trust yourself to do that again?

Pat Gelsinger: Oh my, no! At the time it was great. Of course, when people give me those numbers today, I think they suck, right!? It’s like everybody was trying to break cache sizes and so on with them at the time. Today, it’s no longer a valid view. So I would just yell at our engineers in my last four years at Intel when they would show me SPECint numbers or SPECint rate numbers. That’s code is so old, it’s been so tortured into cache footprints. There’s no longer meaningful view of system performance.

Ian Cutress: There’s a small argument here because I’ll speak to Arm and they still value SPEC2006 because of the embedded market. The embedded market still relies on it. But I completely understand your point.

Ian Cutress: Going back a little bit for a second when we have these agentic setups, I often see that a lot of people are playing with it but it seems a very personal implementation on people improving their workflows. I struggle to really see where it’s going to offer it at scale - and the the only sort of workload I’m seeing where it is actually being applied at scale is because our good friends at Synopsys and Cadence are leaning on it heavily than almost anyone else.

Ian Cutress: So how do we bridge that gap? Is that just a time thing or is that just a familiarity thing?

Pat Gelsinger: That’s a great place to start - so let’s just say that’s wonderful. But there’s a whole lot of other engineering workflows other than that, in material science, CFD, and now we’re worried about hypersonics, so there are just all sorts of wonderful things that open up across the greater EDA space, not just chip design.

The explosions that are happening in bioengineering - now you’ve created orders of magnitude of additional complexity as you start looking at three-dimensional molecular models. You can’t make the nice 2D simplifications like you can in a lot of the chip design flows.

So I do think we’re at the beginning of these processes, not anywhere close to the end. And I do think that every one of these, as you open one up, somebody’s going to be the one that jumps ahead, and then what happens is sort of like cockroaches - there’s a little bit of food in that corner, and a lot more industry innovation will run in that direction.

Ian Cutress: Given your background and it relates a little bit to my background on the HPC side, I speak a lot with the people over there on almost on a weekly basis and they’re getting frustrated by the whole march of machine learning. Especially as we look at 64-bit precision being reduced in traditional accelerators and I know that a lot of them are wary of 64-bit emulation in the 8-bit side. Do you have any good news for them? Or whatever your opinion is on it?

Pat Gelsinger: Well, a couple of thoughts. I mean, when people started talking to me about BF4 (4-bit brainfloats), I was like, what are you talking about? You know, I was worried.

I was worried if 64 bits was good enough. We needed the 80 bit modes that we put into IEEE854 for the precision. Now we’re saying that four bits is good enough. And I think even there, people are doing interesting work, but what they find is, models actually don’t settle very well when you get to a precision that low. So useful bits seem to be more in the 8 to 16 bits range for most model work. I’m not a model expert in that regard but they sort of run some of those benchmarks at four bits, but the reality is most machines aren’t actually operating there. Emulating 64 bits in a 16-bit environment is very different than saying we’re going to do it in the four-bit environment.

But I do think as we move to the next phases of science, and not just doing large language model performance, as we move to the next phase of science, where the LLM almost becomes a leaf node, not the core computational node, you’re going to be back to worrying very much about precision. So I think there will be, over the next couple of years, the revenge of the HPC guys!

Because now when I want to start using LLMs in the context of a CFD for my airplane or hypersonic design, I’m going to be fusing these together and I’m not going to be able to give up precision for this portion of the workload. Even though the LLM portion may be perfectly happy running on a BF8 machine, I’m going to need them both. So I do think the next phase of application of AI, is going to be increasingly in the science domain, increasingly in three dimensions, not in flatter language representations. And as a result, all this pursuit of getting to four bit, two bit, etc, I think some of that’s going to be for naught, because the real machines are going to be combining those together in a much more central way in workloads.

Now maybe I’m just trying to convince myself that all that hard work I did on 64-bit and 32-bit floating point is going to come back to reality! But I think it’s based on the view of workloads. The next phase is not doing more language modeling, it’s much more science modeling, and as you get to science, I need real precision to look at many of those algorithmic domains. Again, it comes back to the workload.

Ian Cutress: Speaking to a few people who run university supercomputers they’re saying, because of the price of accelerators these days and the high demand, they’re almost seeing cloud computing be more cost effective. If there’s one thing you don’t want, it’s a student accidentally clogging up a thousand GPUs in the cloud with bad code. I think they’re struggling and as you mentioned them before. You know, our friends at NextSilicon are trying to solve part of that. I think there’s a community who really want more love.

Pat Gelsinger: I think so as well. Remember, NVIDIA began its journey into AI through the HPC door. So I do think there’s going to be good science being done there. I think the National Labs matter a lot. I think some of the government programs matter a lot here, and people like NextSilicon I think will be helpful. But I do think there needs to be more networking work.

I joke that NVL72 is an engineering marvel and a manufacturing nightmare, right? How do you build those things, scale them? You’re hitting just the limits of copper, we saw a bunch of optical conversations. I think we need new models that become resilient networks, like we’re doing with Delos Data, so that we create more flexibility in the underlying network, because we can’t have the failure rates that we’re seeing today for these super large configurations.

Then you’re just spending all your time either restarting and redoing or checkpointing, right? And that’s not a computing architecture suitable for a lot of the workloads that we want to get to. So I do think some of these things are going to move us more rapidly to optical, move us more radically to resilient networks, more radically back toward dataflow machines with the full gamut of precision. And then of course we’re going to do radical things like Snowcap, which are just a 1000x times better.

Ian Cutress: I’ll go speak to people like IBM with the Z processors and then some of the automotive players, and they speak about resilience as a very hardware focused element. Yet with Delos Data and others we’re seeing it more as a software application on top of the hardware. Is there a right balance?

Pat Gelsinger: I think the workload again is the determinant. In the sense that, hey, if the software has assumed faulty hardware, and has built resilience into the software layer, then software is the right answer. But if in fact a whole lot of workloads, sort of the difference between a virtual machine and a Kubernetes machine is who is taking care of resilience? In the VM, I’m assuming the hardware is, and I’ll run any software including containers. In the opposite view I can only run containerized software because I’m not presuming resilience in the hardware. And for a lot of things, hardware is better for resilience, right? I can see memory errors, I can correct memory errors, I can see link failures...

Ian Cutress: But it costs die area that I could spend on another ALU...

Pat Gelsinger: You certainly could, and I think now as we’re looking at machine learning and the failure rates we’re seeing, we need more resiliance in the hardware. It’s not resilient enough anymore for some of these incredibly large cluster sizes that we’re seeing emerge. So I don’t think there’s a one size fits all answer to that question. I do like Jensen’s co-design perspective here, because there are certain things that I think are done better in software resilience, but there’s a whole lot of things where you don’t let the hardware guys off the hook. You’re going to build five nines hardware. You’re going to be able to prove 10 to the 12th, 10 to the 14th, error rates. And until your material structures have proven that, get back in the lab and finish your freaking work, right? To prove something that I can really build on into the next generation.

Ian Cutress: Last time we recorded one of these, it was at Intel Foundry Connect, I’m sure you remember. It was all about the Five Nodes in Four Years. How much do you spend these days thinking about next generation foundry and packaging technology?

Pat Gelsinger: Well, obviously here at Global we have investments in Xlite, so I’m spending a lot of time on how we build next generation. Or as I call it, waking Moore’s law up from its nap..

Ian Cutress: So it’s not dead?

Pat Gelsinger: No, absolutely not! I think we’ve put it on an economic pause, because transistors haven’t gotten cheaper. I can still build more of them, but they’re not cheaper anymore. And they’re not as effective of a powerful tool as they have been in the past. That said, Xlite are bringing a better light source to EUV, enabling us to think beyond today’s 13.5nm of light, moving and solving the stochastics, the polarization...

Ian Cutress: You really think there’s going to be something less than 13.5nm?

Pat Gelsinger: Absolutely!

Ian Cutress: I think I disagree.

Pat Gelsinger: Oh why do you disagree?

Ian Cutress: I don’t think I’ll see anything beyond EUV in my lifetime. Because of the stochastics, because of the energy!

Pat Gelsinger: Oh, but we could take, with a free electron laser, I can give you so many more photons, right?

Ian Cutress: Yes, but in terms of making it commercially viable at scale?

Pat Gelsinger: Absolutely, not the slightest hesitation in my mind. We’re going to pull that off over the next decade. Absolutely the case. And whether it ends up being in the 7nm range, in the 4nm range, absolutely, there will be a next generation wavelength of light. It’s going to be at much, much higher power levels. Free electron lasers can produce 2000, 3000, 4000 watts of delivered energy, which allow you to radically reduce the stochastics. Even if you apply that only to 13.5nm, you get a big win in the yield characteristics. I’m going to be able to go from double patterning to single patterning, so I get more productive in my capital efficiency.

Ian Cutress: But if you can’t reflect, and it means you have to scan the wafer vertically in order to do it.

Pat Gelsinger: Hey, there’s going to be new material structures that, we’re going to innovate. So absolutely, you know, you skeptic for the advancement of science and new materials. This is going to be thrilling.

Ian Cutress: It’s not I’m an absolute skeptic - I’m just pulling on my material science background.

Pat Gelsinger: Okay, for your audience here, you and I are going to take a bet right now that we will see wavelengths below 13.5nm in the next decade in production deployment.

Ian Cutress: Okay, in mass production, yeah, a dollar is always a good bet. I always bet a dollar.

Pat Gelsinger: Yeah, you know, pick your favorite bottle of wine, or favorite thing that you like, you know, whatever it is because you’re paying me buddy.

Ian Cutress: We’ll see!

Ian Cutress: We recently saw a startup promising what they call X-ray, and I was doing the mathematics, and the video on it might actually be out before this because we’ve just done the final cut. I spent an hour going through the math of how many photons you need to have compared to EUV for an effective use, and in order to scan and how you produce that. An EUV machine will do 150 wafers per hour, layers, and the best I could get a synchrotron to do across all the beam lines was 40 wafers per day. Per day!

Pat Gelsinger: Okay, well, free electron lasers, we believe we’re going to be able to deliver dose at full productivity, in the equivalent in excess of 2,000 watts, compared to today’s 500 or 600 watts in the EUV machine. They just announced 1,000 watts. So we believe we can go much, much higher. And also the spectral purity of a free electron laser - instead of splattering tin like EUV, we’re producing finely precision light sources as well. This is a pretty magic technology, so that’s one example.

Ian Cutress: A small story, I found the supplier who provides tin for ASML and they wouldn’t tell me anything! I reached out to the supplier and you know eventually worked out that you’re using less than grams per day in an EUV machine. So the cheapest part of the machine is the tin.

Pat Gelsinger: So yeah, I definitely think that next generation light. We see that light also enabling many other aspects of semiconductors, new forms of metrology, new forms of packaging as well. I think it will initiate a whole set of equipment development, as well as new materials development, for mass refraction technologies, new forms of chemistry as well can be improved. If I give you more photons, I’ll be able to move to harder resists, which have natural benefits in and of themselves, not just next chemistry, when I go to 4.5nm wavelength of light. So yeah, I’m an optimist there. And of course, as we’re seeing just extraordinary capital investments going into today’s level of machines, I think people will start to see “Oh, there’s real value in some of the critical layers moving beyond that.”

Ian Cutress: Here’s another one of my critical points and I want to cite the the work that was done on 450mm wafers, you know, the 18-inch transition. You know, as well as I do between IBM, Intel, and others, this whole consortium came together, solved it, and then the industry turned around and said, yeah, but it’s going to cost us a trillion dollars to transition, so we’re not going to. I have a great picture of me holding one of those 18 inch wafers, and I asked IBM, can I have it? And then we realized there may be export restrictions on it. Do you think about that when you’re you know considering the next phase of semiconductors?

Pat Gelsinger: Oh absolutely, you have to think about the adoption. The insertion point in volume supply chains, what’s the capital requirements to move it into volume deployment, what will be the business models be associated with it. One of the things with the Xlite business model is we’re going to move to photons as a service.

Ian Cutress: Oh no! That sounds terrible!

Pat Gelsinger: Well, I call it God said, “Let there be light,” right? Light as a service. And just like today, you have chemical supplies sitting outside of the fab and energy substations out of the fab, you will have light substations out of the fab. It’ll become a utility going into the fab. And that has so many benefits, right? I use different pools of capital to go accomplish that, I’m not burdening the fab with the capital requirements. Also, that’s very long life. I can keep upgrading the free electron laser. I can attach it to many different types of equipment, metrology equipment, packaging equipment, lithography equipment.

Ian Cutress: Assuming you can bend it?

Pat Gelsinger: Oh yeah, not that hard, right? Grazing incidents, mirrors and other things that are pretty robust technologies. So we see this entering into a next phase of how you build much, much higher productivity into the most expensive capital equipment industry on earth, the semiconductor. We have to bring capital efficiency to the semiconductor industry if we’re going to continue to have this dramatic expansion that Moore’s Law was enabling. It took a nap, and now we’re going to wake it from its slumber.

Ian Cutress: I’m seeing this interesting dichotomy here, because on the one hand you paint a very vivid picture about the future of where we are in semis, whether that’s architecture, whether it’s manufacturing. But then also it’s the ‘solve the problems of the day’, right? That’s where the business is. It’s all very well having your blue sky investments, but realistically you still need to make money today, not just tomorrow. Do you find that now, in this new stage in your career, you’re favoring one more than the other?

Pat Gelsinger: Well, I’ve always been a tech guy - a deep tech guy. So I’m sort of drawn to those 10-year projects. But I also realize I have to have a portfolio that investors can look at, and we have limited partners as well. So I need some that okay, this is going to be a two or three year win solving a today problem.

A company like PowerLattice that we announced, that one’s going to be much faster because that is a today problem. And some of the other power related companies, I think those will have two to three year cycles that’ll give me some time to work on my 10 year cycles as well. But even there, a company like Snowcap, I think we’re going to have real commercial use cases around that in two to three years. As dramatic as superconducting logic is, the fact that satellites happen to operate in 4 Kelvin space. Saying I have a 2 or 4 Kelvin superconducting, it’s sort of a native ambient environment and I don’t produce any space so I don’t have to radiate any heat. that’s actually pretty good.

Ian Cutress: Well, or anything you do radiate is a larger proportion of what could affect it?

Pat Gelsinger: Yeah, so that’s pretty clever in that regard.

Also every quantum project will want more things sitting in the cryogenic temperature range. So all of those projects will want more of what we’re doing with Snowcap, and there are some nice problems that fit beautifully into a smaller logic. All the signal intelligence problems, give me smaller footprints of compute where I don’t need as much memory, they’re going to fit nicely into it.

So I think there’s going to be great commercial applications even before we hit the big wins of creating AI inferencing centers that are a 1000 times more energy efficient than today. That’s the holy grail, but there are some really good milestones along the way for commercialization.

Ian Cutress: So what does it take to get on Pat Gelsinger’s radar?

Pat Gelsinger: Well, being super smart, right? People who have really worked on problems, like the Snowcap team, they have worked on that problem for 20 to 30 years, deeply in academia or national labs. They have really deep expertise on problems that are meaningful. If we solve that problem, wow, that matters. And then having real views - fusion for example, not one that I’m particularly excited about, because I need 10 billion dollars to prove it, right? Versus okay, I can get $50 million to prove critical technology milestones. Those are dramatically different problems. So we like those kind of problems where we can say, boy, we have tangible milestones that allow us to get to the point where I have to go raise billions of dollars, but I have something that I’ve proven, and now I’m ready to go raise the billions of dollars. I’m not afraid of the billions of dollars, but I want to have proof points along the way.

Ian Cutress: And that’s obviously a point where governments start mattering.

Pat Gelsinger: Absolutely.

Ian Cutress: So, how often these days are you having to interact with the Administration?

Pat Gelsinger: Yeah, quite regularly. Xlite was the first recipient of the CHIPS Act under this Administration, so quite excited about that. We have a number of other BAAs in process, the new process for the CHIPS Act, from our portfolio companies, but also other governments as well are interacting. For example Japan, they do a whole lot in the semiconductor industry, so working with them. A number of our companies leverage Australia - PsiQuantum, half the team was from Australia. I have a packaging company that we’re forming out of Australia doing 3D packaging technology. Some of them are out of the UK, and we have presence for one of our companies in Germany. So it really is across the spectrum, leveraging non-dilutive capital where governments see critical roles for them. So there’s a good amount of that, and I say the network I built with the CEOs of the industry, combined with many of the governments, somewhat gives Playground a pretty unique perspective as we’re in this next phase of taking some of these really cool companies and scaling them to be things that change the world.

Ian Cutress: I know back at Intel, one of your things was to reinvigorate the American semiconductor industry. I assume it still matters, but it sounds like you’re being a bit more holistic now.

Pat Gelsinger: Yeah, I’d say yes to that, but also yes that I’m still deeply committed to reinvigorating the US semiconductor industry. I’m a US citizen. I consider myself an American dream, a farm kid becoming CEO, leading technology - that’s the American dream coming to reality. I feel a deep loyalty to the nation in that regard. I helped to bring the CHIPS Act into existence. And I do think the absence of explicit industrial policy by our government renders us at risk as a nation.

A brownout in Taiwan has an economic impact that is twice as great as the Great Depression. A brownout, right? Remember, Taiwan has three weeks of energy reserves on the island. This is not a stable situation for the world’s supply chains of technology. I want more of that in the US. I want more manufacturin g in the US. I want more of our supply chains for critical minerals, semiconductors. We’ve radically underinvested in the energy capacity of the nation. For a decade, one to one and a half percent increase in the energy capacity of our nation. We spent so much time preoccupied on renewables, we forgot that the only thing that really matters is how much. There are 39 nuclear reactors being built in China today. How many in the US? Zero. 39 compared to zero. That’s terrible, right? Just terrible.

Ian Cutress: If I recall China last year in March stood up 90 gigawatts of solar?

Pat Gelsinger: Yeah. But again, they’re investing in their energy infrastructure. In the AI age, energy capacity equals economic capacity. It is critical that we accelerate that. That’s why Alva Energy, our nuclear operating company, is so important. We just brought that company out of stealth. How do we get more from our current fleet, as well as restart the industry to build a lot more as well?

Ian Cutress: Well, you should come to Europe, because what we have more than anyone else is regulation. It’s that interesting dynamic because obviously I’m Europe based, but I spend a lot of time here dealing with companies especially in the Bay Area. I know you’ve highlighted in the past, for example, optical packaging up in Scotland, and there are other facilities in Germany, and Germany is quite a hub for that. But I often find that even with all the investment over there, all the startups I deal with, even if they’re based there, they will slowly migrate to the US.

Pat Gelsinger: Yeah, and I think of Europe as having two problems that way. One is I think it’s difficult, Europe has a lot of low capital startups but that mid-capital range, where you move from tens of millions to hundreds of millions, very little of that happens in Europe. So that capital formation in that critical middle phase of a company is very hard in Europe. And then I think the regulatory domain is ridiculously challenging there.

As a result of that, there are the occasional Arm that pop through, but they’re occasional. Extraordinary support, but then also hurdles that make it hard for them to pop through. And that’s why so many companies, and by the way some of these are coming to Playground, sort of say hey, let’s keep a footprint in Europe but I want my domicile to be in the US or in the Bay Area, because of the vibrancy of the community, the research community, but also just the speed that we can get things done and capital formation.

Ian Cutress: Well, it’s good that you bring up Arm, because whenever people say, well, what does the UK bring to the table, right? Okay, we have Arm, we had Graphcore, whatever the architecture was worth in the end. But I’ve always said the one thing we’ve done well is produce CPU architects and engineers. I know you’ve probably had the same conversations I’ve had with people like Philip Wong at Stanford - part of the difficulty of this industry is bringing in new chip designers, partly because the US is such a software driven economy compared to Taiwan or South Korea. Even though Playground is very much a startup incubator, accelerator - do you do more holistic stuff on how do we get people to become engineers?

Pat Gelsinger: Clearly the UK and Europe have a lot of great things going for it in that sense, and I’m quite excited about many of those, and they continue to produce that. I was also meeting with one of the ministers in the UK recently, and I was highlighting that there’s more quantum based work emanating from Europe and the UK than maybe anywhere else in the world. Why should Quantum Valley, if I analogize that to Silicon Valley, be presumed to be in the US? I do think there’s a lot of these major new technologies that are going to be impactful for the entirety of the world, that are yet to be developed, and where will those centers be in the world? I think many of them could be there. I think it takes capital formation. I was recently having a conversation with one of the ministers in that regard, they gave me their initial proposal for how much capital they were going to put behind it, and I said 10x.

Ian Cutress: I think they just announced two billion this morning or something.

Pat Gelsinger: Anyway, 10x that. I said 10x what they originally said to me, and then you’re demonstrating to the world you’re serious. At that proposal it’s sort of like, oh okay, that’s nice!

Ian Cutress: I was at a Ministry of Defense sort of conference and they asked me to keynote, and I did the wave of new AI hardware. We had somebody from Adiabatic Computing, somebody from Quantum Computing, and then at the end of the day there was a Q&A and they said, well, the government just issued a billion dollars for new semiconductor investment. Where should we spend it? And a billion dollars just isn’t enough to fund startups. It isn’t enough to restart any sort of manufacturing or wafer production. And so my response was invest in people - to which the response was that we do invest in people but then they move to the US. I said, well, what if you don’t invest in people and they stay? So my question is, what can we do to invest in people? I mean, it’s all very well having AI and chip design meaning you can design a chip with 15 people rather than 500, but we still need chip designers.

Pat Gelsinger: Well, I do think there’s a lot of great raw talent there. And when you think about the Oxford/Cambridge core.

Ian Cutress: I’m not even just speaking UK, I’m speaking about getting more chip designers in the US too.

Pat Gelsinger: But the reality is there is a wave back toward hardware. There is this enthusiasm again. How many AI dating apps do we need, right? There’s just been such a move to software, to SaaS, to different application things, but all of a sudden hardware is getting cool again. And I think that’s being recognized in our universities and in the startup community as well.

Some of my friends leading some of the big venture firms - one of them confided in me and said, I think we forgot how to do hard, right? And to me it’s like, but that’s where you started! How did you lose your heritage, your foundation? And I think now you’re seeing that whole resurgence come back, whether that’s physics, material science, chemistry, biology, chip development, manufacturing sciences as well. That renaissance of activity in that space is starting to emerge. And I’m super excited. Some of the universities that have never walked away from it, like Purdue, are now viewing this as a West Coast, Bay Area location. For them, they never walked away. Some of the great schools, Stanford, Berkeley in the area, MIT on the East Coast. To me, it’s the resurgence of the hard, the material science, the hard engineering sciences. This is our day, again.

Ian Cutress: So, what does 2026 look like for Pat Gelsinger?

Pat Gelsinger: Well, I want to have several good exits of our companies!

Ian Cutress: Have you had an exit yet?

Pat Gelsinger: Not one that I’ve led, but obviously the recent announcement with Ayar Labs was a nice step forward, along with a couple of good exits from our portfolio companies. I want to do six to eight foundational investments this year, companies that really matter, and then key milestones of some of the next rounds of our companies, bringing them to that next phase of reality. And clearly on my Gloo side, putting a platform in place that really starts to scale the faith ecosystem.

And then I’ve got eight great grandkids, so we’re enjoying time with them and our family. I have more freedom to invest in them and their lives. And then of course I have about a dozen philanthropies that I spend a lot of time on, so seeing some of those milestones as well. I have a lot of wonderful things happening in my life.

Ian Cutress: So you’re getting the grandkids into semis, that’s what you’re saying?

Pat Gelsinger: We’re working on it!

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

I want to speak directly about a situation involving a former employee and recent legal filings. This is not something we take lightly.

In January 2026, SemiAnalysis terminated an employee due to severe misconduct. The former employee demeaned coworkers, came to work drunk, refused to work with certain SemiAnalysis employees, caused repeated workplace disruptions, made an inappropriate sexual comment to a coworker referencing another Company employee by name in a demeaning and sexually explicit manner, and engaged in other misconduct.

SemiAnalysis filed suit against this former employee in San Francisco on Friday, March 27th 2026 for breach of contract, trade secret misappropriation, and other claims. On the following Tuesday, the former employee then filed a meritless lawsuit against SemiAnalysis.

We want to be clear: SemiAnalysis unequivocally denies these claims, and we will defend against them vigorously.

Our suit is available here: CGC-26-635328

Edit: This article has been edited to clarify the timeline. SemiAnalysis filed first.

One of the more recent tour deforces in the semiconductor industry today is the analyst firm SemiAnalysis, headed up by CEO Dylan Patel and a team of around 50 employees all aimed at providing reports and models for the AI ecosystem - everything from datacenter build-out to supply-chain economics and deployments. The firm is relatively new on the stage, but quickly gained significant notoriety for its in-depth analysis and strong opinions, that over time was backed by substantial research. The substack for SemiAnalysis is the front facing part of the business, but the ca$50m+* revenue the company pulls in is mostly from selling its quarterly industry reports and other data features such as its InferenceX benchmarking and rating system for AI companies and datacenters. It’s at a point where Dylan and SemiAnalysis are referenced directly in NVIDIA keynotes and by people like Jim Cramer.

*This number has big error bars. I’ve tried to extrapolate it from data I once knew was correct…

The reason I’m writing this post today is because of a filing made in San Francisco County’s Superior Court. Former employee Wei Zhou is suing SemiAnalysis for, among other things, breach of contract and wrongful termination.

These are court filings CGC-36-635374.

The crux of the matter claimed relates to how SemiAnalysis obtains its data for its reports. Firms like SemiAnalysis have to build reports based on data that is technically public. That doesn’t mean it’s freely available, for example if a company hands me a document or a presentation and tells me that it’s not under an embargo or NDA, that’s public information, but it’s just not widely distributed. Firms like SemiAnalysis obtain their data by filing information requests, looking through public shipping manifests, supply chain documentation, government documentation, or in the case of datacenter build-out analysis, even obtaining permission to fly drones over sites in order to get high quality images of what equipment is being used.

Zhou’s filing against SemiAnalysis boils down to the fact that when given material non-public information (MNPI) and told to incorporate it into the SemiAnalysis models that were then sold to clients (financial and in the semi industry), he refused to do so on the understanding it would break several laws. Zhou claims that as a retaliatory measure, Dylan/SemiAnalysis promptly fired him from the business, removing all access. To make matters worse, the MNPI was related to a $50m investment vehicle that Dylan Patel was in charge of personally, and Zhou highlighted that SemiAnalysis team members worked on this were doing so in company time. Zhou highlights that SemiAnalysis President, Doug O’Laughlin, had duties to stop the use of MNPI, but claims he was too busy fundraising for Patel’s investment vehicle.

The filing has several causes of action.

• Breach of Contract

• Breach of Implied Covenant of Good Faith and Fair Dealing

• Retaliation in Violation of Labor Code §§ 98.6 and 1102.5

• Wrongful Termination in Violation of Public Policy

No specific relief is requested at this time, however the filing indicates over $35,000.

The other wrinkle in this filing is that Zhou was hired to build SemiAnalysis’ highly successful Tokenomics platform. Prior to Zhou’s employment, this did not exist, and in the filing Zhou claims that it was due to his expertise that it got of the ground - the success of Tokenomics lead to Zhou being one of the few employees to receive revenue share. It is explained in the filing that Dylan Patel is the sole owner of SemiAnalysis and there are no stock options/equity sharing with employees, highlighting the revenue share arrangement as a more unique situation within the company. Zhou has not directly requested relief based on this revenue share in this filing at this time.

In order to get ahead of this filing it new was coming, SemiAnalysis has filed a claim against Zhou, CGC-26-635328. The claim calls for a declaratory judgement and restitution based on:

• trade secret misappropriation,

• conversion,

• breach of contract,

• breach of fiduciary duty,

• interference with prospective economic advantage,

• interference with contractual relations, and

• defamation.

In the introduction of this filing, SemiAnalysis claims that Zhou was terminated based on his professional conduct, citing, workplace disruption, inappropriate comments, alcohol issues, and refusal to work with specific individuals. The filing also claims that Zhou claimed his profit share worth was millions, with SA countering that Zhou’s employment contract would only pay should he remain employed by 1st April 2026. The filing goes on to state in no uncertain terms that ‘Zhou should have read his contract more carefully / Zhou’s allegations are [] in an attempt to extort money’. It also claims that Zhou has been making defamatory statements to SemiAnalysis customers and that Zhou still maintains in his possession a company laptop with trade secret information. The complaint later goes on to state that in order for SemiAnalysis to build its array of Trade Secrets, it enforces endpoint security on its employees devices, including encryption and multi-factor authentication such that only authorized personnel can access.

The SA filing is longer than Zhou’s filing, so I won’t go through it all here. It does have a lot more spicy language, claiming to quote direct messaging between Zhou, Patel, and other employees both privately and in company slack channels.

Some Background

I’ve known Dylan for a good number of years, despite him being more than 10 years my junior. Before he started SemiAnalysis he was a moderator on a popular forum where my content was shared frequently - he grew up reading my hardware analysis. After college and moving into the world of semis, Dylan and I have had many conversations and dinners over the years at events.

While we’ve never worked together in any formal financial capacity, Dylan has appeared on my YouTube channel a couple of times, causing some amount of distress for certain Analyst Relations people.

Dylan and I still sync a couple of times a year, at events and such, usually to talk a bit of shop but usually in a very casual way. If anything these days, I’m asking how how business is run, and it’s always changing every time I ask.

By contrast, I’ve only know Wei for a year or so, and only through his work at SemiAnalysis. But we’ve had dinners a couple of times, and in recent months we’ve spoken more often than I speak to Dylan. He’s a smart dude, I can tell. Even then, our conversations are still more about general industry things and memes than anything else.

I don’t really have an ending for this. Like you all, I’m going to keep abreast of the highlights over the minutiae, but it will be interesting to see where this ends up and if it sets a precedent if it isn’t settled out of court.

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And on a personal note, I want to thank everyone that has signed up and remained signed up over the last couple of months. I’ve had a fair amount of travel of late, but I’ve also had some significant family life adjustments as well taking my time and my mental health. It has kept me from posting as much as I’ve wanted. We’re coming up to the financial season again, so I’m hoping to publish a number of pieces on the quarterlies.

I also now have writing some articles for me - he has some contributions in the pipes (some of which are late due to my availability to edit) but I hope you’ll enjoy those as much as my writing as well.

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

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In December 2025, as we covered at the time, NVIDIA acquired the Groq engineering team and a license to use the technology. Although unconfirmed, it was cited around $20b at the time. We covered it on this substack.

At the time, we covered several reasons why NVIDIA made this ‘acquisition’. (I’ll call it an acquisition from hereon, just to simplify things.) We knew Groq was in the process of taping out its next generation chip, but it had missed deadlines set by Groq CEO Jon Ross at the time. With the demands for agentic AI and Mixture-of-Experts models, the SRAM limit of Groq, while high on memory bandwidth, meant that tokens per watt were unfeasible for any large installation without a specific customer in mind. However, today, at GTC 2026, Jensen is showcasing the integration of NVIDIA with Groq’s latest chip.

Groq LP30

The new chip is called the LP30 - Jensen calls this a third generation chip, although as far as we know this is still Groq’s second chip. There might have been a failed tapeout at the startup during those seven years making this the third. But Jensen gave some details.

The new Groq chip looks as if it has the same, or similar, architecture design as the first generation. It is built on Samsung LP4X, and features 500 MB of SRAM. That’s just over double the first chip, but isn’t that much of a bump to be honest. We also see that it has FP8 performance, in this case 1.2 PFLOPs. No power is mentioned, however I’ve seen one analyst quote 600 W per chip. I can’t confirm that.

The chip is going to be in a system of eight chips, in a system called the Groq 3 LPX.

This means eight chips has 4 GB of memory, but the full LPX system will have 256 chips in a 128 GB configuration. It’s worth noting that’s less than a single mainstream GPU AI accelerator that feeds the largest models. Each 8-way rack will be controlled by an FPGA backed by what looks like an Intel CPU. Bluefield-4 provides the scale, with NVIDIA confirming that Ethernet is used to speak to other systems.

The goal is to be able to support higher throughput. Jensen pulled out this graph.

On its own, Rubin systems would not stretch out to 800-1000 tokens per second, and using Groq helps NVIDIA to get there. NVIDIA sees that area as an ‘ultra’ token offering for people willing to spend $100+ per million tokens. I’m seeing this year that code generation (see Cerebras and OpenAI’s partnership) is one such workload where people are prepared to spend that much, or more. One of my key issues this year is the value of a token - no point making tokens if they’re not worth anything. I’d love it if CEOs would talk more about it, rather than simply token generation.

Anyway, one other aspect that came up is how the Groq chips will be used - in decode.

I believe we’ve covered workload disaggregation on the substack before, but the simple way to approach it is to consider most transformer based language models can be split into two parts: prefill and decode. Prefill is a compute bound workload, relying more on raw compute compared to memory bandwidth (but it still needs it). Decode by contrast is memory bandwidth bound. The idea is that Rubin is a happy mix of both - it provides incredible compute and incredible memory bandwidth. Last year, NVIDIA announced Rubin CPX, a GDDR-based chip specifically to address prefill as it was compute focused rather than memory (GDDR vs HBM). Groq is here to address specifically the decode, given that the SRAM bandwidth is a big multiple over what a standard Rubin can do (150 TB/sec vs 22 TB/sec on Rubin Ultra).

In order to enable this, NVIDIA are leaning on its Dynamo platform. Dynamo is designed to be flexible in its parallelism but also when addressing heterogeneous compute. If a customer has a set of Rubin, Rubin CPX, and Groq LPX, Dynamo is aimed to split the workload across that hardware to optimize the throughput given the batch size and parallelism. That’s how we get that graph above. Jensen on stage said that installations could be built with up to 25% Groq chips. They’re set to ship in Q3 or 2H. Both were mentioned.

The question is though, how many chips are required for the big trillion parameter models? Is this for that? 128 GB of SRAM for 256 chips isn’t a lot, even at FP8, but perhaps for code-gen, only 70B parameter models is enough. Even if it’s agentic.

Former Groq CEO Jon Ross has a fireside chat later today. We’re not expecting more architecture info, although there’s an outside possibility. Because I wasn’t given a press/analyst pass this year (see here for info), I won’t be able to attend. But I have people I know in that talk, and I’ll see what they have to say.

Here’s the roadmap. While Jensen did accidentally say Opteron instead of Oberon (hey, it’s a brand name that sticks in the brain), we do see some new information on here:

• There will be a Groq LP35 with NVFP4 support, and a later generation of LP40 in line with the Feynman generation.

• The post-Vera CPU will be called Rosa.

• Feynman will use die stacking and custom HBM.

• NVIDIA will be co-designing copper and optical scale-up solutions simultaneously. This includes CPO versions of NVLink in NVLink 8.

• Oberon will have an ETL256 version, and Kyber will have an NVL1152 version.

There’s more to come no doubt, and I’m on the ground today to find out what. Later this week I’ll be at OFC, the optical conference, so stay tuned for coverage from that as well.

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

On Tuesday, Intel announced that Board Chair, Frank D. Yeary, is stepping down on May 13th. Dr. Craig H. Barratt (not to be confused with former Intel CEO Dr. Craig R. Barrett), who is the former CEO of Atheros Communications and an Intel board member since November 2025, is set to take over the role at the Annual Stockholders Meeting. Yeary has been on the board since 2009 and has held the chair since 2023. Intel’s board will reduce by one as a result.

Per Intel’s own 8-K filing, Dylan Martin, a senior editor at CRN, outlined that Yeary had informed the board of his plans to retire the Friday previous, so while the announcement by Intel is the public confirmation, this has been in motion for at least a week. Yeary has spent 17 years on the board, and has sat on the top step across some of the most difficult stretches Intel has had to navigate in its modern history. Stepping back now, with the company in the middle of a genuine reset, is a significant moment. Investors privately have been discussing the composition of the Intel Board, and are generally approving of this change.

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Barratt only landed on Intel’s board as an independent director in November 2025, so getting the chair role this quickly is fast by any reasonable measure, but his background makes it easy enough to see why Intel felt comfortable moving at that pace. He ran Atheros Communications as president and CEO for eight years, from 2003 to 2011, taking it through its IPO and then its acquisition by Qualcomm, staying on afterwards as president of Qualcomm Atheros before eventually moving on to something different. That something different turned out to be Google, where from 2013 to 2017 he was a senior vice president running Google Fiber and a wider set of internet access and energy infrastructure projects, the kind of operational scale and organisational complexity that the chip industry on its own rarely produces.

After Google, Barefoot Networks came along, where he was CEO of a networking semiconductor company doing genuinely interesting work on programmable switch silicon, right up until Intel acquired it in 2019. He left Intel less than a year after that acquisition, which is worth knowing, and Intel later killed off Barefoot’s Tofino network switch business altogether, which makes his return to Intel in a governance capacity one of the more quietly interesting subplots of today’s announcement. He currently serves as Lead Independent Director at Intuitive Surgical and sits on the board at Astera Labs.

Intel’s CEO Lip-Bu Tan made a statement about the transition, calling out Barratt’s “deep semiconductor expertise and a strong record of technology and operational leadership in complex, engineering-driven businesses.”

Dr. Craig H. Barratt, Intel’s new Chairman of the Board, joins on May 13th

It is worth being straight about what a board chair appointment can and cannot do. Appointing Dr. Barratt does not solve all ills, it doesn’t fix a process node, or close a deal. It does not accelerate a tape-out or pivot the company. What it does do is send a signal, and right now, Intel needs to be sending the right signals to several different audiences at once.

The company is showcasing that the Intel 18A family of nodes (18A, 18A-P, 18A-PT) are set to perform well enough in yield and parametric yield, then in customer silicon, to demonstrate that the foundry business as an IDM is real and not just a strategic aspiration. External customers are currently probing Intel’s ability to deliver on technical specifications and volume production - it is expected that Dr. Barratt can speak the technical language to Intel’s engineers, customers, and investors simultaneously, and having someone with Barratt’s specific technical and operational credentials sitting visibly at the top of the governance structure is part of how Intel constructs that argument.

It also fits a pattern that has been building over time. Intel has added four new independent directors since 2024, and reduced the board overall, as part of what it describes as a deliberate board refresh, and each addition has tilted toward operational and technical backgrounds over purely financial ones. Under Lip-Bu Tan, Intel is trying to reorient itself back toward being a company at the head of the competition.

Yeary’s departure, for its part, is being framed by Intel as a natural transition point, now that the financial stabilisation work of the past couple of years has largely been completed and a clearer technology roadmap is in place. That framing may be accurate, but what is also true is that Yeary has been through some genuinely difficult years, with criticism as well, and the company is now in a different phase, one that arguably needs a different kind of oversight at the top.

The new chairman of the board, Craig H. Barratt, formally takes the chair on May 13th. The real measure of this period in Intel’s history will come when 18A yield data and external customer commitments start becoming visible to the outside world. No board restructuring changes this, but Intel is at least putting people in places for what it is trying to do next.

Intel’s Board currently stands as (with current/former companies noted):

• Craig H. Barratt: Barefoot Networks, Google Fiber, Atheros

• James (Jim) J. Goetz: Sequoia Capital (VC), Palo Alto Networks

• Andrea Goldsmith: Professor of ECE at Princeton, Quantenna, Medtronic

• Alyssa Henry: Square CEO, Amazon, Microsoft

• Eric Meurice: ASML CEO, Dell, Arm, NXP, Soitec

• Barbara G. Novick: Blackrock Co-Founder

• Steve Sanghi: Microchip CEO, Waferscale Integration, Mellanox

• Gregory D. Smith: Boeing CFO, American Airlines

• Stacy J. Smith: Former Intel CFO, Audodesk, Wolfspeed

• Lip-Bu Tan: Intel CEO, Walden International

• Dion Weisler: HP CEO, Thermo Fisher Scientific

• Frank D. Yeary: Darwin Capital Advices, Paypal

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

• This is not new silicon; it’s a better-binned 9800X3D with a bigger boost number.

• The X3D design means there is an L3 cache extension. AMD is world leading in shipping products with hybrid bonding integration.

• Gaming wins are real in mid range, but taper when GPU loaded.

• AI performance is still hard to judge, with GPU vs NPU a hot debate. The problem with AI is still the hardware fragmentation.

• The 9850X3D is slightly faster, but it comes at a cost.

Back at CES 2026, AMD announced just one new desktop chip on its AM5 platform for consumers to feast on. Almost everything at that show was seemingly focused on AI, and while AMD refreshed its mobile portfolio, the gamers were asking about graphics and desktop. Insert the new AMD Ryzen 7 9850X3D.

On paper, it is a Ryzen 7 9800X3D with boosted frequencies - an 8-core chip with extra cache that boosts to 5.6 GHz. Those clock speeds are impressive for an X3D part, and mirror previous mid-cycle refreshes, but the expectation is that the faster frequency will bring improvements to gaming performance. X3D chips have been heralded as the new standard for leading edge gamers, and this one is designed to be one of the best.

The TL;DR is that the wins the X3D has are too easy to misunderstand. Everyone treats 3D V-Cache as a universal upgrade path, regardless of purpose. What’s not to love about having extra memory and saving a few trips out to the now expensive DRAM market?

As you’ll see in our testing, the charts look great in CPU-bound games. The X3D brings significant benefits to gaming performance in CPU-bound scenarios, where a larger L3 cache delivers a significant boost in titles that leverage it.

But it struggles to bring the same value-add to other areas. This is the eternal dichotomy of upgrading one degree of freedom with specific benefits. Really good in one spot, same-same in others.

Honestly, that’s what this review is really about - not whether the 9850X3D tops another set of cherry-picked game charts, but whether the combination of higher binned silicon with higher clocks and stacked cache produces a faster and better-behaved CPU across the board. There are scenarios in here where X3D excels above the competition, but there are areas where adding large pools of L3 cache doesn’t move the needle, and that has to be considered when buying into AMD’s X3D platform.

This isn’t really about focusing on a victory for AMD and 3D V-Cache, but more about whether it can dominate more than just one specific corner of the benchmark universe. Games that are CPU-limited and cache hungry? Sure, it’ll really hit the mark. But in everything else, it has to show that it can deliver in these areas, too. To get there, I’ve treated the 9850X3D like a desktop CPU first and a gaming chip second.

On paper, AMD presents a familiar recipe, and that’s kind of the point. The Ryzen 7 9850X3D is still an 8-core X3D gaming workhorse for AM5, built around Zen 5. It’s a good chip in isolation, and great that AMD is leaning into higher frequencies without changing the fundamentals. But the measure is in what the tradeoff is for the extra 10% in cost.

Ryzen 7 9850X3D Specifications

• Architecture: Zen 5

• Codename/platform: Granite Ridge (AM5)

• Cores/threads: 8 / 16

• Base clock: 4.7 GHz

• Boost clock: 5.6 GHz

• L1 cache: 640 KB (private)

• L2 cache: 8 MB (shared)

• L3 cache: 96 MB (shared)

• Default TDP: 120W

• Memory: 128-bit, up to DDR5-5600, up to 256 GB, UDIMM only

• PCIe: PCIe 5.0

• PCIe lanes (total/usable): 28 / 24

• Supported Motherboards: A620, X670E, X670, B650E, B650, X870E, X870, B840, B850

• Integrated Graphics: RDNA 3.5, 2 Compute Units, 2.2 GHz

• Launch Date: 29-Jan-2026

The headline for AMD is a 5.6 GHz boost frequency, a +400 MHz bump over the Ryzen 7 9800X3D, while keeping the rest of the package broadly intact. This isn’t a small change for an X3D part either, because historically, X3D parts have traded off high frequencies for better cache behaviour in cache-sensitive tasks such as gaming.

For those unfamiliar with the concept of large caches like X3D, it doesn’t make a core run faster in frequency. The concept is that it causes the core wait less often because more data is a shorter time away. The win here comes from avoiding DRAM trips when a game’s workset spills beyond the current cache. These benefits tend to show up in low and overall tighter framerates. In workloads that are compute-bound, additional L3 cache doesn’t really add anything to the mix.

X3D is a physical technology - it’s a design crafted by packaging an extra slab of SRAM onto the compute chip, so a workset has more room to stretch before it trickles over into the DRAM. Compared to previous generation AMD X3D designs, such as the Ryzen 7 5800X3D, AMD has flipped the order of the two chips in the package, placing the cache on the underside of the compute die. This means the hot cores are at the top, and can dump heat into the heatspreader or IHS more effectively. That’s pretty much the real reason AMD can effectively bump up clock speeds without changing the fundamentals of X3D and its packaging. It does have added complexity though. You can find out more by watching our video here:

X3D also has a side benefit, especially in the current DRAM pricing environment: it makes memory speed matter less than it does on a non-X3D chip. When you have a much larger L3 pool right next to the cores, the CPU has fewer reasons to go to DRAM in the first place, so the usual obsession with the fastest and largest-capacity DDR5 kit is less important. AMD states DDR5-6000 is the sweet spot, slightly above its rated box speed.

Before we get to the benchmarks, here are our test benches for AMD and Intel. As we start ramping up our testing, this initial batch is limited based on access, but will improve over time.

AMD Test Bench

• Zen 5 CPUs: Ryzen 9 9950X, Ryzen 7 9850X3D, Ryzen 7 9800X3D

• Zen 4 CPUs, Ryzen 9 7950X, Ryzen 9 7700X

• Motherboard: MSI X870E Gaming Carbon WIFI

• Power supply: Corsair HX850W

• CPU cooler: Noctua NH-D15 G2

• Graphics card: Sapphire AMD RX 9070

• Memory kit: G.SKILL 32 GB (2 x 16GB) Trident Z5 RGB DDR5-6000

• Memory operating mode: Rated speed for each chip

• Storage: Samsung 9100 Pro PCIe 5.0 SSD 1 TiB

• Operating system: Windows 11 (25H2)

Intel Test Bench

• CPUs: Core Ultra 9 285K, Core Ultra 5 245K

• Motherboard: GIGABYTE Z890 Aorus Elite WIFI ICE

• Power supply: Corsair HX850W

• CPU cooler: Noctua NH-D15 G2

• Graphics card: Sapphire AMD RX 9070

• Memory kit: G.SKILL 32 GB (2 x 16GB) Trident Z5 RGB DDR5-6000

• Memory speed used in testing: Rated speed for each chip

• Storage: Samsung 9100 Pro PCIe 5.0 SSD

• Operating system: Windows 11 (25H2)

As this is the start of a new testing suite, we are in the process of defining our hardware and workflow. Welcome to the first set of benchmarks!

Regarding benchmarks, we broadly split into four sections.

CPU Peak Power

The first is power consumption, and we use a simple peak power test. This will be something we’ll investigate better over time, ideally over multiple frequencies and voltages, but due to timing we only have peak power for now.

Starting out with the power consumption of the CPU. Because the X3D chips are often lower clocked than the non-X3D versions, this is often an area where efficiency comes into play. Typically, we see AMD chips performing in and around their respective TDPs, although with our chip it did pulls around 10% more power than the 9800X3D, both rated at 120W TDPs. One would surmise that the extra boost to the core boost speed means it consumes around 12 W more power at peak; it’s whether this additional power and frequency bump translates to performance across the board.

Machine Learning

Next is AI testing, for which we bring in MLPerf Client, which is quickly becoming a very useful tool to judge consumer-grade machine learning tasks. A big thank you to our compatriots over on the team there, including Scott Wasson and friends, for making the client version so easy to use and applicable.

The two main metrics for machine learning is TTFT (Time to First Token), ie how quickly the model responds, and TPS (Tokens Per Second), how fast it does respond after that initial hump.

Looking at MLPerf and using the Phi 3.5 Windows ML benchmark, the clear benefit of Intel’s NPU in the Core Ultra (Arrow Lake) series of processors is evident: time to first token is around 5.4x faster than on every AMD chip tested. This is because the NPU can be used here - AMD only has the integrated graphics.

On AM5 desktop parts, that “Radeon Graphics” block is essentially a display-first iGPU: two RDNA compute units (128 shaders/stream processors) intended for desktop output and media, not heavy GPU compute, so there’s parity across the Ryzen CPUs here, but not parity versus an NPU-accelerated path.

Analyzing tokens-per-second performance, the narrative is flipped. Intel wins the time-to-first-token hard, but once generation is underway, AMD chips run around 25-30% faster than Intel chips.

A key point here with the Ryzen 9 9850X3D (and 9800X3D) is that the addition of 3D V-Cache (64+32=96MB) doesn’t provide any performance benefits for AI workloads, because the optimized path is through the graphics. Even the Zen 4-based Ryzen 7700X is a whisker behind the Zen 5 cores here, showing that Windows ML does not benefit from the uplifts associated with core architecture.

In future with this test we also will be aiming to report power for a performance/token metric.

CPU Performance

The CPU core testing combines a few common tests that a lot of reviewers use, such as Cinebench 2026, Geekbench 6, and Blender 4.5. We are in the process of integrating SPEC2017 into our workflow, but were unable to arrange it in time. Expect to see it in future reviews.

Cinebench 2026 single-threaded is still a clock and front-end-heavy contest, and currently Intel’s 285K sits around 3% ahead of the Ryzen 9 9950X. In terms of the Ryzen 7 9850X3D, it’s around 4% slower than the 285K, while the increase on boost with speeds of up to 5.6 GHz offers around 2% additional single-threaded performance than the Ryzen 7 9800X3D.

Transitioning to Cinebench 2026’s multi-threaded benchmark, it’s mainly a test about core count and bigger cores. AMD’s Zen 5-based 9950X (16C/32T) proves more effective than the competition, with the Intel Core 285K slightly behind (8P+16E). For the Ryzen 7 9850X3D, the performance gains are marginal, with a boost in boost frequency yielding just over 1% additional performance. It’s a reminder that stacking L3 cache isn’t really beneficial for compute-heavy tasks and workloads.

In Geekbench 6’s single-core benchmark, the Ryzen 7 9850X3D tops the list, even edging out the 9950X by around 1.4%. It also shows an uplift of around 5% here over the Ryzen 7 9800X3D. It’s prevalent because Geekbench tends to reward short, turbo-heavy boosts rather than consistent, sustained throughput.

Geekbench multi-core brings things back to the expected hierarchy of multi-threaded performance: AMD’s Ryzen 9 9950X wins out, Intel’s Core Ultra 9 285K comes in second by around 3%, but the real takeaway here is that the Ryzen 7 X3D pairing (9850/9800X3D) is effectively tied. There’s a noticeable uplift over the Zen 4 8C/16T 7700X, which is expected given the generational gains from Zen 4 to Zen 5.

Blender 4.5 is more about pure throughput than anything else, and it treats the X3D chips in an unbiased fashion; performance between the 9850X3D and 9800X3D is virtually identical. It’s another way of saying that stacking L3 cache doesn’t help in pure grunt and rendering throughput.

Both Zen 5 X3D chips also perform around the same level as Intel’s Core Ultra 5 245K (14C/14T), which, given Intel’s cheaper MSRP of $309 compare to AMD’s $400-499 pricing of the Ryzen 7 X3D chips, shows Intel offers better value here in rendering throughput.

Discrete Gaming Performance

Then for gaming, we pair the processor with a high-performance graphics card and we have a few select titles and resolutions up for comparisons. Each of our CPUs here is paired with a Sapphire AMD RX 9070 16 GB graphics card.

Benchmarking Civilization VI at 1080p Ultra is a good reminder that X3D isn’t an automatic win in all things gaming. The non-X3D Ryzen parts sit at the top, with a noticeable performance advantage over Intel’s Arrow Lake pairing. Comparing the two Ryzen 7 Zen 5-based X3D parts, the 9850X3D is under 1% faster than the 9800X3D. We saw better 99th-percentile performance on the X3D, with the additional frequency giving a small boost on the 9850X3D.

At 4K, where graphical grunt from the graphics card is more important, performance is led by AMD’s 16C/32T offerings, both in average and 99th percentile frames. Both X3D chips perform virtually identically here, while Civ VI is a good indicator of which brand it favors: AMD over Intel.

In Company of Heroes 3, the cache-laden X3D chips win out here, although just marginally over Intel’s flagship Core Ultra 9 285K. The difference between the X3D chips is marginal (0.3%), indicating that the extra core speed doesn’t deliver meaningful performance gains here.

At 4K ultra, Company of Heroes 3 is generally GPU-limited, although there is a noticeable performance uplift from Zen 4 to Zen 5.

In Total War: Warhammer 3, the X3D peaks again demonstrate their value in kind, with a sprawling, simulation-heavy workload that places heavy cache pressure on the system. At 1080p, both the 9850X3D and 9800X3D sit clearly ahead of the pack, with better average performance than the 9950X and around 15-18% ahead of Intel’s Arrow Lake parts. In 99th percentile performance, things weren’t as peachy as average frame rates, although still up there with the other chips on test (bar the 7700X, which lags behind pretty much consistently in overall performance).

At 4K, there’s literally no difference among the chips in testing, which is typical for a GPU-bound scenario at higher resolutions.

Price vs Performance

The 9850X3D is the simplest kind of CPU refresh on paper: it has the same 8-core Zen 5 X3D layout as the 9800X3D, the same cache stack, and the same AM5 platform, but is binned to hit a higher boost target on the core frequency. That makes it a good opportunity to not entirely ignore headline clocks, but to place greater emphasis on the behaviour when running workloads, and to look at what actually changes in practice.

My aim here is to show how the chips behave under sustained load, what voltage and power it takes to maintain the all-core frequency, and whether the extra performance is efficient or just expensive. Using matched 10-minute Cinebench 2026 multi-thread runs, the charts below focus on the deltas between the 9850X3D and 9800X3D in power, Vcore, clocks, and temperature, and what that means for performance-per-watt.

On the Score vs average package power plot, the story is quite brutally simple: the 9850X3D is buying a tiny score bump with a pretty big watt increase to achieve it.

• 9800X3D: 5531 pts at 113.6 W avg

• 9850X3D: 5622 pts at 141.0 W avg

This means the Ryzen 7 9850X3D achieves a ~1.0% performance uplift in exchange for operating at 24.1% higher power. If you want a single “efficiency” figure from that chart, points per watt show the following:

• 9800X3D: 48.7 pts/W

• 9850X3D: 39.9 pts/W

Now this looks somewhat absurd on the face of it. But the reality is, even within these chips, we don’t know if we have a ‘good version’ of one and a ‘bad version’ of the other. It’s something other testers are also seeing - some have larger power differences, others have next to zero. But on this data alone, it would imply that the Ryzen 7 9850X3D is around 18% less efficient in Cinebench 2026 MT under a sustained CPU-only, non-cache heavy workload. The behavior that differentiates the chips is exactly what we would expect to see from a higher-binned SKU under an all-core load.

The 9850X3D runs at a faster all-core frequency of 5.25 GHz, compared with the 9800X3D at 5.19 GHz, a 1.1% increase. This is at a cost of a higher V-core curve, which we observed at 1.257 V on average, a large 10.4% bump over the 9800X3D at 1.139 V.

Operating at a higher CPU VCore effectively means two things: it draws more power at the package level and runs hotter. The extra 27.4 W drawn by the higher-binned 9850X3D yields only an additional 91 points in Cinebench 2026 MT, at the cost of running around 11°C hotter.

That’s for a CPU-only workload, but what about during gaming?

In the above plot chart, there’s no real difference in average frame rate performance between the two at 1080p ultra settings in the Company of Heroes 3 benchmark. We do however, observe that to achieve parity in average framerates, the 9850X3D is pulling a whopping 74 W on average, which equates to 2.96 FPS per watt; but the 9800X3D is 41% more efficient with 4.18 FPS per watt, with an average package power draw of 52.3 W. Compared to multi-threaded workloads, gaming isn’t as intensive on the cores, so temperatures are both below 50°C here, but the 9800X3D not only runs around 8°C cooler, it averages a much lower CPU V-Core and is 42% more power efficient to achieve virtually identical frame rates.

On Cinebench 2026 multi-thread performance per dollar, the 9800X3D is simply the better buy. Its 5531-point score at $444 works out to 12.457 points per dollar, while the 9850X3D’s 5622 points at $499 drops to 11.267 points per dollar. Put another way, the 9800X3D delivers about a 10.6% value advantage, which makes the 9850X3D’s small score gain hard to justify once the price increase is factored in.

On Company of Heroes 3 at 1080p Ultra, the performance-per-dollar picture is even more one-sided because the actual FPS result is basically a tie. The 9800X3D posts 218.6 FPS at $444, which works out to 0.492 FPS per dollar, while the 9850X3D manages 219.2 FPS at $499, or 0.439 FPS per dollar. That tiny 0.6 FPS advantage doesn’t come close to justifying the price bump, which leaves the 9800X3D at roughly a 12% better value in this specific game test.

Overall, the Ryzen 7 9800X3D is a considerably better value proposition than the 9850X3D right now; that extra $45-55 in savings could be put towards memory. The DRAM market is turbulent at the moment, affecting all desktop platforms. Right now, DRAM is being tugged in two directions. Demand for AI infrastructure is causing the companies that need it to bid directly on supply, pushing up the price. That has a direct effect on the overall cost of building a new PC, so opting for better performance per watt and performance per $ is crucial to delivering value to consumers.

On a straight score-per-dollar basis, the Core Ultra 5 245K is the value standout here at 19.84 points per dollar (5813 for $293). The Ryzen 7 7700X isn’t far behind at 18.49 (4623 for $250). From there, it drops off pretty quickly once you climb into the high end, where you’re paying a lot more for smaller gains. The Core Ultra 9 285K comes in at 16.22, while the Ryzen 9 9950X lands at 14.19.

The most relevant comparison in this section is between the two 8-core X3D parts. The 9800X3D works out at 12.59 (5590 for $444), and the 9850X3D slips to 11.34 (5660 for $499). Same takeaway as the efficiency charts: you’re paying extra for a marginal bump, and on multi-threaded performance per dollar, the 9850X3D is simply the weaker buy right now.

For users looking for the best CPU grunt for their money, Intel’s Core Ultra 245K is the best buy, while the 9800X3D is the best value pick for gamers, especially for CPU-bound games at lower resolutions. The last-generation Ryzen 7 7700X, based on Zen 4, is also a solid pick for compute tasks, though our gaming results place it well below the other chips tested.

DDR5 pricing has been a top topic lately, making selecting DRAM one of the most annoying parts of budgeting a desktop build. One week, a sensible 32GB kit looks fine; the next, it has jumped just enough to make you stop, double-check, and start that mental shuffle of where the money should actually be spent. The problem is, users need DRAM to make a system work, and for new builders, there’s no way to avoid the market volatility, which can completely change the whole conversation about value.

Conclusions

Across the compute and gaming results, the Ryzen 7 9850X3D is only fractionally ahead of the 9800X3D, roughly half a percent in compute and about two-thirds of a percent in gaming overall. The wins are real in a couple of single-threaded tests, but they do not translate into a consistent uplift in heavier rendering or real-world gaming at higher resolutions. The awkward bit that we have to unfortunately focus on is power: peak draw rises from 119 W to 131 W, so you are spending about 10% more power to buy roughly 1% performance, and the efficiency maths just does not work in the 9850X3D’s favour. It feels as if the Ryzen 7 9850X3D is a flex on binning rather than an upgrade over the 9800X3D, despite the 400 MHz boost to 5.6 GHz; the 9800X3D tops out at 5.2 GHz.

It’s also worth being very clear about what X3D is doing here, too, in terms of performance. The cache still helps where it has in the past, with CPU-bound games seeing an elevated boost in both average and 99th-percentile frame rates. In compute-heavy applications such as rendering, there’s no noticeable difference between having a 3D V-Cache and not having one; it doesn’t affect performance here.

The practical conclusion is a simple one: the AMD Ryzen 7 9850X3D is not a bad chip; it’s just not meaningfully better than the 9800X3D. Unless the price is a sticking point, get whichever chip is cheaper if you’re a gamer, although if you need more compute heavy grunt in a processor, the Intel Core Ultra 9 285K and Ryzen 9 9950X offer much more in multi-threaded performance.

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Some of these limitations are more educational than practical - but some of them lend themselves to performance enhancers like power efficiency or memory bandwidth. Beyond that, while we have ISAs like x86, Arm, and RISC-V, the industry is now full of these - but they all roughly delineate down into very specific lanes. That is why we have a proliferation of software stacks and such that go down each of these routes.

So when a company turns around to me and says, “We’re doing something different and it’s going to accelerate a bunch of things,” I often turn around and say, “Well, show me the proof. What data are you getting? What exactly are you accelerating?”

Insert NextSilicon, a company taking a very different approach. I interviewed the CEO on the run up to their latest Maverick 2 processor launch - but one thing I learned from that launch, even as a semi-insider, is that there are really smart people inside. I like speaking to smart people because they sometimes have funny stories, but they can actually tell us what’s going on underneath - and what they’re thinking at any given time.

So enter Ilan Tayari, VP of Architecture from NextSilicon. I sat down with him at Supercomputing 25 to dig deeper into their new architecture and why they believe it solves the problems of modern high-performance computing, both HPC and AI.

The following is a cleaned up transcript of the video above.

Ian Cutress: Take me back to where you were, seven years ago as a co-founder, and thinking about doing something different.

Ilan Tayari: My background is mostly software. I’m a software guy, but part of my sins is that I used to work for Mellanox. In Mellanox, I had to go deep into the hardware features and understand the hardware architecture. One of the things that I learned about hardware is that pipelining things is part of making it go fast. That is when the idea occurred that you can take an application and pipeline it.

CPUs and GPUs are based on the Von Neumann architecture that you mentioned, which is eight decades old and is not new in any way. All these CPUs and GPUs are doing the same thing. When you run your software on these architectures, you are taking C/C++ code and compiling it. Compilers - and you can see this in LLVM practically - they use an intermediate representation which is a graph. This graph represents dependencies between the operations. Then, you take that and serialize it into an instruction stream. The silicon in the computer core reconstructs the graph. It has to reconstruct the dependencies and see what depends on other things and what does not in order to reorder them.

Ian: It does that line item by line item?

Ilan: Yes, but it is more than that. A processor runs ahead of your program, fetches more instructions, and figures out what depends on what. It can issue multiple memory outstanding operations and multiple ALU operations at the same time, not in the order that you wrote the instructions.

Ian: But that means it is faster!

Ilan: Yes, exactly. It is hiding the sensitivity to the latency of the core. Now, what if you could do away with all that? Simply take the graph, the intermediate representation, and make hardware that executes that. Then you get something that is pipelined without the overhead of reconstructing the graphs. Why do the lowering and then the lifting if you can just pass through that and bypass the transformation? Then you get something that is more efficient. It is at least as performant, if not more, because it doesn’t get things wrong in the sense of ordering, and it is much more efficient because it doesn’t have to deal with instructions.

Ian: I’m going to play devil’s advocate here and say that when I write and run my code, I don’t necessarily care or see what is happening down the chain, but I know there’s an underlying instruction set architecture (ISA). When you are saying you are running a graph, surely you are also converting that graph into some lower ISA for it to run on the chip?

Ilan: When you say ISA, it is a term that has a lot of connotations. People think about an instruction set encoded like x86, RISC-V, or Arm, where you have some kind of encoding for each type of instruction and they come in a stream. But when you compile, the intermediate representation, it’s made out of operations that are laid out logically in a graph, and you don’t have to serialize that into a stream of instructions.

I’m talking about hardware that can run the graph directly by configuring different elements. Let’s say you have an element that does addition, one that does shifting, and memory access obviously. You just lay them out with the connections. Once they are laid out, you don’t need to stream instructions back and forth. There is no instruction stream. There is no instruction fetch. There is no reordering of instructions.

Ian: I want to think about it mentally in the sense that, yes, when you compile and get down to the assembly level instructions, it is just a linear vector of instructions that get loaded one by one. Yes, you may have dependencies and they get figured out. What you are saying is more from the graph; you can almost turn that into a 2D representation of an instruction stream.

Ilan: Definitely.

Ian: As long as you are smart about where instructions are located within each other. I think one of your diagrams shows that. Even though I sat through the briefings and tried to work with you guys on some of this explanation, I may actually be finally getting it!

Ilan: One more thing about this is that a CPU core, any instruction set core, even a GPU - goes through the instruction stream and reconstructs the graph, and it does a good job at that. But at any given point in time, it is only executing a few instructions, not your whole program, not your whole inner loop.

Ian: This is when we say an IPC (Instructions Per Cycle) of 2, 2.5, or 3, even if it is a 10-wide core.

Ilan: Exactly. Your inner loop might be a complex formula. If you are in HPC (High-Performance Computing), it might be a scientific formula that has a lot of components and a lot of computation. That is more than just two instructions, five instructions, or even more than ten. When you run this on hardware that runs the graph, you can pipeline through this a lot of threads, a lot of context, and a lot of iterations in your iteration space on different stages at different places in the graph. So that every ALU is actually executing every cycle. So now it is not two IPCs or 10 IPCs; it is the whole loop every cycle.

Ian: And that’s where the element of data flow comes in.

Ilan: Exactly. You can only do that with data flow.

Ian: One thing that comes to mind there is that you made a big argument on the launch of Maverick 2 about how a lot of a core is dedicated to dealing with memory, whether it is translating addresses, looking up addresses, and then all the caches involved in that. But in the diagram, you said with our architecture you don’t need such a big MMU (Memory Management Unit) involved. However, you still need to funnel the bandwidth in. Can you describe how that works?

Ilan: There is a lot of secret sauce there, and we have patented one of the things, which is the reservation station and the dispatcher. It takes data that is coming from the memory or from previous instructions and pipelines it into the data flow graph. Moreover, there is an MMU in our system, but unlike a CPU MMU that has to deal with your whole program, ours is different. A single CPU MMU has to deal with all the memory accesses that you have in your program and it uses a TLB (Translation Lookaside Buffer).

In a data flow graph, when you spread your memory accesses around geographically across the chip, every MMU has to deal only with a small set - let’s say 10 or even fewer, like two or four - memory accesses. So a certain memory access instruction in your program has a very different memory access pattern than your whole program. You can optimize that much better than you optimize MMUs in a CPU.

Ian: So that means for the modern codes that we look to run, whether it is anything from HPC - which I know this chip is targeting - or machine learning, we can still get the streaming in. I say “stream” because it is a very common benchmark, but are there any benefits to the bandwidth you can ultimately get out of it?

Ilan: Yes, of course. Think again about the data flow pipeline. Every memory access instruction is part of the pipeline. So you could have a lot of outstanding memory accesses coming from the same element in your code at the same time. They are independent because they are running different threads, so they can be outstanding at the same time. The amount of outstanding memory accesses going to the DRAM or to the cache is much higher than you would find in CPUs and GPUs. It is an order of magnitude higher.

Ian: Do you still get issues like false sharing?

Ilan: Well, it depends on how you do the allocations. Naïve allocations come up with false sharing; you get that. But one of the things about our hardware is that we don’t try to analyze that at compile time and deal with it because that is a very hard problem. Nobody was able to do that. What we do is we collect telemetry, and at runtime, we adapt and change the allocations. So you might have your memory pages or memory blocks allocated at one place, and then during runtime, we figure out that there was false sharing and we move them around. That is why we actually use the MMU because it allows us to keep the virtual addresses and change the physical addresses around.

Ian: When I am thinking about a classic CPU architecture, where you have the prefetch and the decode stage, and a lot of modern architectures have µOp-caches after they have done the decode and rename. Given the nature of the architecture, because you are compiling the graph, that just doesn’t even need to take place?

Ilan: Yes, we don’t have an instruction fetch unit. We don’t have an instruction cache. We don’t need all of that. We don’t have an instruction out-of-order engine or reorder buffer for instructions. We don’t need that.

Ian: As you look at the levers that you can pull for increasing performance in the future, what levers are accessible to you? Because if I look at a modern CPU core, they might say we have a bigger TLB, more prefetch units, better page walkers, more ALUs, more branch units, more load stores and so on.

Ilan: There is so much! But the jargon is so much different than CPUs.

We have certain blocks and they implement parts of your pipeline. Coming up with the correct balance of how many integer units you have, how many memory access ports, the ratios of those compared to memory, how many threads you can have capacity for, and absorbing latency so that the pipelining becomes full throughput. A lot of these things are degrees of freedom that we can play with and customize.

I can tell you that we have done a lot of work analyzing the common kernels in HPC to come up with a mix that is good for everything. You cannot get everything; that is too much to ask for! But we found a good mix that allows us to run a wide range of applications at full throughput at very high performance. The point is beating the competition, and not just by a few percent, but by an order of magnitude.

Ian: As an analogy, if we took a modern CPU core and designed it just for weather prediction for example, you might change the ratios, but it would reduce performance elsewhere.

Ilan: Absolutely. I’ll give you an example. We generate more than one configuration at a time. We generate one configuration, another one, maybe tens of them, maybe hundreds of them, and replace them. The ability to switch from one configuration to another is hardware-accelerated. That is something we have learned over the years.

Specifically for weather simulations, those have hundreds of different kernels. They have hundreds of different physics. There’s the dust, pressure, temperature, things that are going vertically and horizontally - and all kinds of things. It is a challenge generating that amount of different configurations and still switching between them efficiently. Compared to, let’s say, a molecular dynamics one that has only a few where you are going over a loop lots of times. Different challenges in different applications.

Ian: That was one of the questions that came out of the launch - when we look at other data flow architectures, they often define the data flow and it is built into the binary. When it goes to runtime, it just lays it out on the chip, runs that, and cycles through.

You guys said that you can have a configurable data flow while the kernel is running.
That switching penalty that the others have - if you want to call it a penalty or a latency - is low enough on NextSilicon?

Ilan: Yes, exactly. But also note that we are not generating configurations on the fly at microsecond speeds. We generate new configurations every few seconds according to telemetry. When we generate configurations, we generate a set of configurations, and those can be reconfigured on the fly while the application is running at microseconds and even nanoseconds in some cases. So there are two different layers of granularity.

Ian: Your CEO, Elad Raz, is very hyped up that that is one of the key innovations.

Ilan: Yes, it is. As you know, this is Maverick 2. That suggests that there is, or was, Maverick 1! We learned a lot from that. Part of what we learned is that the overheads are very important. So if you have your kernels running for 100 microseconds and your overhead of switching a kernel is 100 milliseconds, that doesn’t work. We have to make it much smaller. That is what we did. We added the required hardware acceleration to get those overheads to the minimum. We have plans to do that even further in the future.

Ian: But I guess if you are being malicious with carefully crafted code, you can make it look like it’s really bad. But the same with any other normal core.

Ilan: You can do that to a CPU as well!

Ian: Yeah, trust me, I’ve done it to CPUs. I’ve done it to GPUs!

Ian: Talk me through going after HPC. Because right now we are in this sort of AI craze with machine learning. I work and cover so many companies in that space where all they are doing is either a mixture of CNN, DNN, or Transformer models. It is interesting to hear your opinion of why HPC was the goal with Maverick 2.

Ilan: Don’t get me wrong! we are not neglecting AI. Of you look at it from the financial point of view, HPC is a very small niche market and the AI market is like three or four orders of magnitude larger. There are trillions over there and there are only a few billion in HPC. We strategically chose to go after HPC for multiple reasons.

One of them is that it is large enough to get the technology to a maturity level. It has the most sophisticated customers and players that can play along and absorb all this. They’re not just willing to learn, they are willing to take the time and effort to optimize, to deal with bugs that happen, and to deal with the wrong architecture and give you feedback that is useful for the next generations of the chip. So they are helpful in that sense. They are almost not customers but partners in the development, and you don’t find any of that in the AI market.

Ian: My criticism for the HPC market, and given we are at Supercomputing, we all love the HPC market, is that sometimes they can be very slow to put in orders. Sometimes systems end up being used by students who are on three, five, or seven-year programs and don’t stick around.

Ilan: That is why in the HPC market we went to the largest and biggest computing centers. As you probably know, we work with Sandia National Laboratories. These guys are the largest national laboratory in the United States. They have seen every possible platform that was ever manufactured and they can give us feedback that is practical. Like: “Applications are doing this,” “Applications are doing that,” “This is what users care for,” “This is the usability that people expect,” “This is the performance that if you don’t have, you’ll get thrown out.”

Some of the things we’re seeing.

First of all, the STREAM benchmark. That’s a very simple thing; it just shows that we are able to utilize the HBM bandwidth.

Then you go to things like GUPS (Giga Updates Per Second), which is a random memory access. This shows you what happens when your cache is completely useless because GUPS is always cache missing. It doesn’t vectorize, it doesn’t coalesce memory, it doesn’t do anything like that. Even in GUPS, we are able to utilize the HBM to the fullest. The numbers we get are unheard of on any other platform on GUPS.

Now GUPS is just one synthetic specific microbenchmark, right? It is synthetic, but a lot of the applications on the defense front, and even in HPC, behave similarly. They have something that is not very regular; the memory accesses are just going around, sparse workloads or something like that. This is an immense benefit that we have that other platforms don’t.

Ian: So do you expect to be compute-bound in most cases?

Ilan: Actually the opposite. I think the compute is so performant that we are taking workloads that are typically compute-bound and making them memory-bound, going right up to the roofline. A lot of the platforms have a certain roofline, and you can see the peak and the memory bandwidth, but they can’t reach the top. Our system and our architecture is able to maximize that and get to the top.

Ian: Are you getting any feedback on that front that’s making them reconsider how their internal code is structured to change that model, to change where they fit on the roofline?

Ilan: Regarding code changes - it is our stated goal to require zero code changes.

But once you do that and you get your portfolio up and running with acceleration, you get the appetite. You have your few champion applications that you want to invest in. There are plenty of things you could do to your code to make it run faster. One of the things that we provide is the tools to identify what is blocking your performance and what is slowing down your application, and recommend changes that you could do to your source code. It just so happens that these changes are often very good for other platforms as well. So if you just refactor your code in this way, you get even better CPU performance.

Ian: People might be familiar Intel VTune and similar software - you’re talking about something along those lines?

Ilan: It’s a profiler tool. You could say it is very different than VTune because the architecture is different, but if you are talking about the user flow, then it is something similar.

Ian: Going back to that optimization on Maverick 2, I understand that by profiling the code, by instrumenting it, the hardware will then dedicate more resources to the parallel parts versus the serial parts. I’ve seen some conversations in the market asking if they right write really bad code, it will work well. Or similarly, if the code is going to be adjusted, how can I optimize for the underlying architecture? Because it is such a different way of thinking against programming for CPUs and GPUs.

Ilan: We don’t do automatic parallelism. We’re not inventing parallelism out of nowhere. You still need to be smart and you still need to express the parallelism in your program. Not necessarily vectors. It could be anything - using Kokkos, CUDA, whatever. You need to express the parallelism in your program. You cannot write bad code and expect it to perform. It will work, but it will not perform.

So you can’t write serial code and expect it to be vectorized. It doesn’t work.

But once you write your code in a parallel fashion, then we can scale up the parallelism and concurrency in the chip.

Ian: So do you have to write it in the SIMD model of GPUs in that way?

Ilan: You could write SIMD code, but also you could write OpenMP code - you could write Kokkos code, you could write CUDA code. Anything that expresses parallelism at the source code level compiles into intermediate representation and we understand what the parallelism is. We take that from there.

Ian: You also advertise a ‘bring your own code’ model. So does it mean it supports CUDA? Does it support the other GPU languages? And given where Nvidia sits on other people using CUDA code, have you had any issues on that front dealing with it?

Ilan: Not yet. We will see how that happens. I think the “CUDA moat” is a problem, but we will see how we can alleviate that. One of the possibilities is to use HIP. Other vendors have gone that way and a lot of codes are being rewritten from CUDA to HIP to bypass the moat. We still have a few tricks up our sleeve! There are legal issues there as well, so I won’t go into that in this interview, but we believe that we can do that.

Ian: Turning to machine learning, I know you guys are planning a future chip that’s more focused on machine learning. How are you viewing that market for your architecture? Because it’s one thing to go after HPC that has to deal with everything and the hardest codes in the world, to something that might be insanely regular or a lot more predictable. Because we were talking about how you change those degrees of freedom to optimize. Can you be a Transformer-specific or CNN-specific design?

Ilan: One thing to say is that the data flow architecture is more efficient. You can take that it is more efficient than a CPU or GPU, even if it’s a CPU or GPU that’s designed for AI. However, if somebody wants to make a chip that’s LLM-specific, inference-specific - even go specific into that, do only FP4, do away with the FP64 - that is going to be more efficient than our chip no matter what you do, because you invest all the silicon in just one specific use case.

If we had more resources and time, we would go about that and make a chip that could be more efficient than the other competitors using data flow, solving a specific problem for a huge chunk of the market. But that would not take us in the direction that we want. So we’re avoiding going there and spending the resources there. Instead, we did a chip that is an HPC chip. We are looking into how we can do AI with that and how we can do a product that’s viable for AI with that.

Ian: But is the intent to still at least maintain FP64 performance?

Ilan: Yes, we are an HPC-first company. There is a lot of interest now in workloads that are HPC+AI. For example, people are training their AI using an HPC simulation.

Ian: I’ve often found that at this event, that’s a very difficult conversation to have with some people who are unwilling to accept that is the way it’s happening.

Ilan: It’s happening! And if you’re looking for a system to run this kind of workload on, then you have to run both a GPU or an AI accelerator as well as your HPC accelerator. The newer generations of GPUs are not good for that. And our chip has a very good potential in that market.

Ian: One trend in this industry is that chip packages are getting bigger. The advent of chiplets means more silicon and ultimately more compute, more power. I noticed that Maverick 2 has that chiplet infrastructure. Is there anything unique in that chip-to-chip boundary or stuff that has to be considered at runtime?

Ilan: Oh yeah. So let’s go to basic principles. You’re saying this as a fact, chips are getting bigger. But did you ask yourself why? Why do people want bigger chips? It’s faster to keep it on silicon sure, but it is more than that. It is faster to have the dies connected together because you have lower latency and higher bandwidth.

But when you scale out, when you make a system, when you design your application and your system in a way that is scaling out, then probably that’s not the main factor. What people want is density. They want to put more silicon in the same rack compared to just taking more real estate, and that eventually comes up into power and OpEx and other factors.

We’re not strangers to that. Our chips are, as you said, going into that. We’re looking in future generations to improve the connectivity further so that neighboring chips can talk to each other and you can scale workloads, and even things like AI when you shard your huge model to do that across chips. Even today you can do that with a Mellanox NIC and RDMA, but you want something more integrated. That’s the way of the future.

Ian: In HPC, MPI is often preferred. Are you doing anything specific for MPI when it comes to multi-chiplet?

Ilan: So in the Sandia system, the Spectra, we have just Infiniband RDMA doing MPI kind of like GPUDirect, when the accelerator is driving the NIC without involvement of the CPU. But we have more tricks up our sleeve.

Ian: Wait, more tricks in that silicon or to come?

Ilan: Both!

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Joining me for this conversation is Mark Papermaster, AMD’s Chief Technology Officer and EVP. Mark has been at AMD since 2011 and has overseen much of the company’s modern engineering strategy, from the early Zen turnaround to Infinity Fabric, 3D V-Cache, Instinct GPUs, and the company’s recent push into rack-level AI platforms. In this interview, we talk about what changed inside AMD over the past decade, how engineering culture and roadmap planning evolved, where AI is reshaping chip design itself, and how AMD is thinking about power scaling, optics, cooling, and modular system architecture going forward.

The following is a transcript of the video interview embedded above. Phrases have been adjusted slightly to improve readability.

Ian Cutress: If I go back through my memory we first met in 2016 at IFA in Berlin, at a time when AMD wasn’t the big behemoth it is now. We were discussing the ins and outs of the market at the time. Given that you now have Ryzen, EPYC, and Instinct, the major product lines driving the company forward, what would you say has changed the most inside the company?

Mark Papermaster: I love that you go back to when we met in Berlin, almost 10 years ago, because it is a perfect capture of our journey. I joined in late 2011, and two or three months later, Lisa Su came on. She ran the business, I ran engineering, then Lisa became CEO two and a half years later. People didn’t realize in that period of time, up until when you and I spoke in 2016, of all of the building that had to go on to create a chip infrastructure that could be there for the AI era.

When you and I spoke, I don’t think almost anyone believed we could be a player in the industry. What I loved about when you and I chatted is you were very receptive; you follow the industry. You were asking, “Why do you think this new CPU, Zen, could compete?” and we talked about the different segments of the market and where it would go. In fact, it did play out that way, and we’ve had a chance to stay in touch over the years.

What has changed in that period of time is that visions turned to reality, both for the industry and certainly what the game plan that we set out to do at AMD. We set out to be a very agile competitor, offering not only CPUs and GPUs but other key hardware and software IPs to be able to be a solution provider, to be able to listen to customers. We now have an incredibly broad portfolio.

What’s happened in the industry since you and I spoke? That vision played out. It was a little bit different: in 2016, we probably all thought the Meta world would be more advanced than it is. We thought that was probably a bigger segment than it is, but we were very much talking about how disruptive AI would be. It has been all of that and more. For the most part, our vision of the industry and our vision for AMD has played out as we thought, but moved even more quickly than we imagined.

Ian Cutress: We’ve obviously had lots of discussions. I speak with the architects, and every time we talk about designing a chip, we have this two or three-year cycle, but then you have five and seven years of pathfinding and working with foundry partners, for example. Going back to then, how much of a “smoke screen” do you think the success of the first couple of generations of Zen was, relative to where the projected nature of the business was going to go?

Mark Papermaster: If you think about what we did with the first generations of Zen - we launched Zen in 2017, it came out in EPYC Servers and Ryzen PCs. You call it a “smoke screen”; I don’t use that analogy. I call that our proving ground years for the first two generations. The questions were: Is AMD for real? Is the value they’re providing real? Will they be a sustained innovator? Will they show up every cycle? Are they that true competitor bringing leadership performance, or are they a flash in the pan?

Ian Cutress: Before the success happened, you obviously have to project where you’re going. Everything’s hyper-accelerated now, but back then - and this is why I say “smoke screen” - at some point, you have to put the pedal to the floor. Was there any of that, or were you able to accurately work with customers and partners at the time to model where you expected to be?

Mark Papermaster: We had our pedal to the floor the entire time! You can’t do anything in this industry but move at your absolute best pace. When we launched Zen, we had banked the turnaround of AMD on having not just a competitive but a leadership processor. It took three generations to hit the knee of the curve on our Zen processor capabilities. Prior to Zen, the core had big gaps in competitiveness. The first generation added 42% instruction per clock.

Ian Cutress: I remember that presentation. It’s one of my key memories.

Mark Papermaster: It brought competition back to x86 CPUs. Since then, we’ve had double-digit IPC gains - significantly, 15% to 20% IPC every generation. So, no slowing down. By the time we hit the third generation Zen, everyone realized: “Wait a minute, AMD is a different AMD. They’re here every generation. They’re delivering exactly what they promised when they promised it”. That’s when our market gains started to really grow.

That’s a turning point for AMD - everyone saw the knee of the curve on technology capabilities and the financial results that came with it. We had always planned to start with CPUs because there’s no barrier to adoption; x86 is x86. If we delivered leadership, it would sell. People didn’t see that we had a GPU effort running in tandem to grow gaming graphics with Radeon, and we’ve always been very focused on AI and bringing GPU compute to market.

Ian Cutress: You mentioned double-digit gen-on-gen performance consistently. It’s the question that gets asked every five years, but given Amdahl’s Law, given Moore’s Law and Dennard Scaling, do you see a limit anytime soon in that raw single-core performance, or are we going to end up being workload dependent?

Mark Papermaster: I love that you asked that question because you’ve asked me that in every interview.

Ian Cutress: I expect everybody asks you that in every interview!

Mark Papermaster: It’s a common question - I love this question. It’s because I never cease to be amazed at the innovation of our engineers. Our CPU team is now a storied team under the technical leadership of Mike Clark. He coined the name Zen.

Ian Cutress: He told us he was called the “Zen Daddy” internally last time.

Mark Papermaster: He’s called the “Zen Daddy” - but it’s not just Mike, it’s the whole team around it. I could not be more excited with where our CPU roadmap’s going. Yes, we’re getting less out of every technology node, but we have an incredibly deep co-optimization with TSMC. For 2-nanometer, we are the very first customer of TSMC - the first tape-out that they received. We highly optimized around that. Although we’re not getting the same energy efficiency gains, we are getting density gains, and that’s very important to drive TCO forward.

You’re going to continue to see yet more density of cores. However, you can’t just bank on density of cores; you have to think about how you’re architecting to keep that balance of CPU computation, memory, and I/O. You need to make sure you have really efficient multiply-accumulate, because AI is everywhere, and everyone still has fleets of CPUs because you have all your legacy workloads. It’s not like they all go to a GPU; they’re going to be around for ages.

We are very excited about how we have modified our AVX engine. Your listeners know we have a dedicated AVX engine. We already run native 512-bit wide, and it’s already a good inferencing engine; it supports VNNI. Then, going forward, you’ve seen we said publicly in our work with the x86 advisory group that we have what we call the ACE engine. It’s an advanced, very flexible inferencing capability that we’re building into Zen 7 and beyond. It’s a super exciting future of CPU computation - not just performance per watt per millimeter squared, but also how you blend in inferencing capability and how you make sure it works seamlessly with the GPUs for heterogeneous computing.

Ian Cutress: Going back a little bit to the beginning, you’ve been at AMD now 15 years, going through that Zen, EPYC, and Instinct ramp. Has there ever been any situations where you’ve had to choose between an A or a B, and perhaps regretted the decision, or actually realized it was really good you did this over that?

Mark Papermaster: Of the latter, there are many decisions that we looked back and said were the right ones. There’s a few that were wrong for sure. But the biggest thing that we did right was the investment, even before we started the Zen core, in what became publicly our Infinity Fabric. It’s our network-on-chip link technology, and it was game-changing for AMD. You could build the best CPU and GPU, but if you can’t connect them seamlessly so they can scale and you don’t create bottlenecks, it doesn’t matter.

We started that investment in 2012, and we’re on our fifth generation of that fabric now. That’s been massively enabling. At the time, it was hugely disruptive - people quit the company. They felt it was the wrong way to go; we had top leaders just get up and leave.

Ian Cutress: I remember Mike saying that.

Mark Papermaster: That was an absolute decision that was game-changing. I’m not sure we would have made that decision if we weren’t in a position to make big bets.

Chiplet technology was a huge corporate bet. It’s paid off incredibly handsomely. In 3D stacking, we’re still the only one in mass production. Think about a gaming chip that has our SRAM or 3D V-Cache; for four years, it’s gone unchallenged because of bringing that memory locality.

We support what I call “healthy contention” in our engineering culture, where people throw rocks at different ideas and we can debate it professionally to make better decisions. We haven’t had huge misses; we haven’t had any micro-architectural visions that we’ve had to say, “Oh, we were just kidding, we’re not supporting that”. The misses we’ve had, if we’ve had something that caused a spin of silicon because of a late-breaking bug, we try to minimise that - we run a deep ‘lessons learned’ on it and adjust our methodology so we don’t repeat it. It’s built into our culture.

Ian Cutress: I remember the story Mike was saying about how the first spin that came back from Zen 1 could only work under sub-zero cooling, and some of the learnings had to be made at that point.

Mark Papermaster: Yeah, we absolutely had some issues on the first pass, but guess what? We worked around each one of them. That’s another thing: you have to build in resiliency. We have reliability, availability, serviceability architected in for robust operation. What people don’t realize is we have a ton of diagnostics and fungibility built in so that if there is something that got through, we can work around it. If it’s found late and it’s in production-level silicon, we can have a very robust production patch so that from an end customer, there’s no loss of functionality.

Ian Cutress: How important is it that an A0 has to work ready for commercial use? And how often do you hit that?

Mark Papermaster: For our GPUs, almost every cycle the A0 is the production target because GPUs are imminently programmable. They’re forgiven that way. CPUs, we’ve typically always designed with two passes in mind, but that’s changed going forward for two reasons. One, it’s an immense cost to build a mask set - so many millions of dollars for each mask set. Part two is building the test samples, because you need to really test across thousands of samples, and that’s also immensely expensive. We need across our whole portfolio to have first-time right.

The great news is AI has now come along, and we’re making great strides with AI across physical design, but where I’m most excited is actually design verification. We’re getting great agentic processes that are improving our coverage. We’re finding bugs earlier. We invested years ago in deep emulation technology - it’s not only important for us to get our designs right but that our own FPGAs are used!

Ian Cutress: How many of those machine learning tools in design and verification are coming directly from your EDA partners versus being built internally?

Mark Papermaster: It’s a mix, roughly half and half. If you look at the synthesis flows and the place-and-route flows, those we absolutely deploy our EDA partner solutions because they’re heavily investing there. But the other half where we have to really invest is our knowledge. It’s the agentic flow - how you take the smarts that you have. We’re a 55-year-old chip design company, and we have the most advanced packaging capabilities and some of the most advanced thermal cooling and power delivery. Those things impact the design itself.

You don’t just 3D stack; you architect for 3D stack. We had to create capabilities to make sure we didn’t have hotspots. So, where we’re cutting edge, we’ll develop the capability that we need. Going forward, we’re going to use the best the industry has to offer, but use our agentic flows with the knowledge capture over many years.

Ian Cutress: Some of the audience may not realize that you actually spent 26 years at IBM. You were working on a variety of things, including IBM Power. The tools we’ve just spoken about are obviously very new. Are there any common threads you can draw from those 26 years of experience that have come through your career to today?

Mark Papermaster: I was so lucky to start when I did. It was early ‘80s when I graduated and started with IBM. I started with a small renegade team that was tagged to create IBM’s first NMOS and then, two years later, their first CMOS ASICs. There was no EDA industry then. Our customer at that time was the IBM mainframe, which drove tremendous advances in technology. I learned to make multi-chip designs even back then.

I started as an analog person, then quickly went into digital and microprocessor design, and led Power microprocessor design. Analog taught me that you can never lose sight of the physics. Even though you have all the advanced analysis tools, it always came back to: Does the physics make sense? Is the science behind it sound?

What it really taught me from early on is the importance of cross-disciplinary innovation. It was the dawn of the EDA industry so it was bringing in advanced tooling and automation into chip design. Because we were a small integrated group, we had to work closely with the fab, so co-design with the foundry. I was ‘probes down’ on wafers, taking measurements.

The lessons from the ‘80s and ‘90s couldn’t be more applicable than today. Think about why BiCMOS changed over to CMOS: because BiCMOS drove too much power. Here we are running up against power limits again and having to innovate through those walls. The lesson I took away is, anytime someone tells you, “We’re dead,” “there’s a barrier,” or “Moore’s Law is dead.”, it’s the innovation that rules. We find ways to move around those barriers and provide end customer value.

Ian Cutress: So, Moore’s Law is not dead?

Mark Papermaster: Exactly!

Ian Cutress: It’s interesting you bring up your experience like that because a person we both know, Philip Wong at Stanford, has often lamented the fact that students today don’t have the same opportunities, or that the jobs in the industry aren’t being pivoted more towards chip design and physical design. Is there any opinion you have on ways that we can change that?

Mark Papermaster: I actually just saw Phillip and in the last couple of weeks we chatted about this. There actually is starting to be a return to hardware interest. Everything had shifted to software, but we are now seeing more students interested in hardware. But, Ian, it’s completely different now. We are promoting an AI-native approach to chip design at AMD. It’s thinking about chip design with AI as your right hand - just like you wouldn’t go anywhere without your phone - it’s an indispensable tool. AI is a productivity tool, and to reimagine chip design as AI-native from the outset is going to be incredibly disruptive over the next five-plus years. I think how we practice chip design today is going to completely change. Of course, we’re aiming for first time right - the kind of computation we’re building up to do AI training, that same computation can do AI for science. It’s going to disrupt the industry - we’re going to be able to get a much tighter marriage of silicon to algorithms.

Ian Cutress: Does that not create a risk of if the algorithms change, the silicon is worthless?

Mark Papermaster: Well, that’s why we continue our investments in general purpose CPUs and GPUs! People always jump to the conclusion that because custom design gets 40% more performance on a given workload, everything will shift there. Actually it doesn’t, and for the very reason that you stated - there’s a constant change of algorithms. So, you’re always going to need general purpose computing.

We believe that the tent is so large that there’s room for tailored specialized solutions even while you need the general programmability going forward. We have FPGAs so you can prototype and adapt to the latest algorithms. And for big customers that need a tailored version of silicon, we’re happy to do that and leverage our advanced packaging and foundry partnerships.

Ian Cutress: You’re saying that this tent is very broad, and one of the things that AMD’s done this year (2025) has been acquisitions - I think almost a dozen companies, several thousand employees, most of which have fallen under your organization. The question then becomes, does AMD have enough? Will there ever be enough engineers?

Mark Papermaster: It’s changing. First of all, as CTO, I work with all the teams. I’m very fortunate to have that role, and when you look at the skill acquisitions we’ve done, we’re very focused. Most of it has been AI model development, and a set of skills we needed with photonic and optical development. But the biggest acquisition this last year was ZT Systems, which gave us true rack scale design. You don’t have to look beyond next year’s Helios rack - we showed it off at OCP this year, and you can see the benefit of that tight partnership. Our competitors who looked at it said, “Wow, that is a true co-design”.

Going forward, you need deep co-design with the foundry. Now, for true AI training and large model inferencing, you have to have that same partnership with the top hyperscalers and model developers. We’ve earned that seat at the table. To optimize, you have to be skilled all the way through rack design. For the biggest AI compute capabilities, we now provide rack reference designs.

Ian Cutress: How much of that Helios design was done pre-acquisition, and was ZT Systems involved in that at all?

Mark Papermaster: They were. We were on a path to acquire, and it takes about a year to close these things. We created a set of agreements; the way it works is they have to be able to survive if the acquisition doesn’t go through. We put all that in place and created that deep co-design partnership. If you go back in time, we had already been working with ZT for years, and got a strong appreciation for their design and manufacturing capabilities. We already had a set of agreements in place. What you see in Helios is a result of true co-design.

Ian Cutress: Did that accelerate when money got involved?

Mark Papermaster: You say money, but what is money? It’s about having a leadership AI cluster design. Everyone knows the industry is going to quickly, so the carrot out there is huge already.

Ian Cutress: Going back to POWER, we went through a time of being shocked at 90 watts per core, 120 watts per core. Now we’ve got multi-core coming along: 128 cores, 192 cores, and 500 watts per chip. We have AI chips hitting a kilowatt, two kilowatts, and you’ve seen the same predictions I have going to six kilowatts to ten kilowatts per chip. From an engineering perspective, does that worry you?

Mark Papermaster: It’s like I said earlier - it drives different innovation. Some people look at it and say, “We’re clearly going to hit a power wall, and innovation will stop”. No, it drives innovation.

We are shipping 750-watt GPUs today, on our way to kilowatt and two kilowatt designs and beyond. It’s spurring tremendous innovation. In the last two weeks I’ve met with startups and seen university research on heat spreading and heat removal technology. At IEEE last month the lead article was on a diamond heat spreading technology that’s pretty amazing. So there’s a lot in the development pipelines that will help here.

What you’re going to see in the immediate term is those that need dense clusters will all adopt tightly integrated liquid cooling. That’s becoming a de facto standard for dense racks. It’s a problem to overcome; but it’s not a barrier, but you have to co-architect it.

Ian Cutress: The funny thing is speaking about IBM before, they actually did a lot of work in the ‘90s on intra-chip cooling.

Mark Papermaster: Oh my! Those mainframes I referred to earlier - each chip sat on a “pogo stick,” which was a heat removal thermal conduit. If you take inflation into account, that was a pretty expensive design approach! But it just tells you: engineers innovate; engineers solve problems. The new approaches will be much more economical than back in the ‘90s to do equivalent highly efficient heat removal.

Ian Cutress: You’re talking about these racks being tightly coupled co-design. But if we go back to the IBM mainframes of the ‘80s and ‘90s, the irreducible unit was the mainframe. When we look at rack scale today, we have CPUs, and GPUs, and optical connectivity. We designed them in a different way.

Mark Papermaster: Today, it’s much more modular than it was at that time. We’re committed to modularity at AMD because it expands our addressable market. If we tailored the GPU or CPU compute core only for data center computation, we couldn’t address enterprise needs, edge computing, or all the way down to PCs. We are running 100-billion-parameter models on AIPCs today.

From our perspective, we wake up every morning thinking about how to architect across that scale. We have people that wake up every day thinking about vertical optimization, focusing on rack scale. Then we have other people who are thinking horizontally. They create that healthy contention and say, “I love what you’re doing for rack, but if you did a slight change, we could derive that in a very fast way to address the other markets we serve in AMD”. It goes back to our conversations back in 2016 - that modularity is a huge part of our history today, and it’s an even bigger part of our opportunity going forward.

Ian Cutress: When we look at the next several years, everyone’s talking about bandwidth, whether that’s intra-chip, chip-to-chip, or chip-to-memory. One of the things I’ve been focusing a lot on is the optics realm, especially co-packaged optics. The route to optics is very top-of-mind for the big GPU players. What’s your opinion there, and how should we frame it mentally?

Mark Papermaster: The way to think about optics is: why is it only prevalent in scaling out massive clusters in data centers, and not scaling up the densest clusters? The reason has been cost. Copper has done the trick. Helios is a 72-GPU node design using copper; it’s cheap, reliable, and you have to architect that in, but it works great. But as you go beyond 72 nodes and start getting the scalability into thousands - thinking of Mixture of Experts approaches - you want bigger and bigger cluster sizes.

The good news is, photonics in the next several years will tip over to be economically viable. The supply chain is coming up. You will see photonic solutions phase in where you need very, very dense nodes. But copper won’t go away because you have such a range of solutions. Think about all the enterprises out there that do not need foundational model training. Think of photonics as coming on board in the next three years, all the pieces of the supply chain coming together, starting at just the biggest clusters.

Ian Cutress: From a technical standpoint, can you design a product that can switch in and out optics versus copper, or do you have to go down the optical route for definite?

Mark Papermaster: You can architect for both. You can architect in flexibility.

Ian Cutress: Most of the discussion today is chip-to-chip, but we’re seeing some solutions today talking about optics to more banks of HBM, a sort of chip-to-memory expansion. How much of that is on your radar?

Mark Papermaster: Well, we follow it all. Celestial.ai has just announced that Marvell will be acquiring them, and they’re working on solutions like that. We think that’s a fine solution, and congrats to David and the team, we think it’s a fine solution. AMD is all about an open ecosystem. We encourage all these types of innovations because it gives our customers more choice. We’re not about a solution that’s proprietary and is all AMD top to bottom. For us, it’s about getting the best compute elements out and having multiple partners that can piece that solution together. The next 3 to 5 years are going to be very exciting around photonics.

Ian Cutress: How much has stress increased moving to this yearly cadence on compute?

Mark Papermaster: We were already on an annual cadence for PCs and consumer gaming. Our EPYC CPUs have largely remained on an 18 month cycle. We knew what it would take to move to an annual cadence. But the pace of AI is torrid, and it’s driven by customers who just need that type of improvement. Whether it’s new math type formats or elements of that nature, it just needs that pace, and that’s what we’ve done. We found we had to understand the pinch points and beef up staffing in certain areas. It’s where we’re focused on applying AI into our chip design practices - on the chip points that facilitate that annual cadence.

Ian Cutress: That’s obviously very customer-driven. How does that affect your pathfinding? How do you still innovate when you’re on the treadmill of getting designs out so quickly?

Mark Papermaster: That’s a common concern. Some companies have said, “We’re going to have a half a day every Friday for innovation,” but I haven’t found that to be effective. What we have found is you have to have innovation built into the design process. So rather than rush that design phase up front, we have pathfinding teams, and it starts in research. We have a very strong research team, and it doubled in size when we acquired Xilinx. Xilinx was also committed to an open ecosystem just like AMD, so that came beautifully. So pathfinding starts there. If you think about the most advanced work on CPU, GPU, and AI algorithms, it’s in a five-year plus timeframe for the research team.

But we don’t just have an ivory tower research team that’s just looking at five years and beyond, part of that team is in the three-to-five year, and they’re working with the development teams that are getting out the next generation Zen CPU or Instinct GPU. Then, at the high-level design phase, we want to give the teams the time to make sure that they have the right innovations to be competitive. We have a well oiled roadmap process, it’s one of the things that Lisa and I put in place back around the time we first talked, or even earlier. We put in a philosophy of these ideas also solving a customer issue and having a business team to pair with them to ensure it also matches a market need. We give our teams the agility to innovate, but when we approve a project, it has to have the rigor behind it. We need our projects to all deliver and return what they promised to the company.

Ian Cutress: For 2026, can you give the audience the thing that you’re most looking forward to?

Mark Papermaster: 2026 is going to be really exciting from a couple of fronts. At AMD, we couldn’t be more excited about what our next-generation Instinct GPU brings, because with that Helios rack, it brings us smack dab into full-scale training and inference. We support training today, but it’s to the thousands of nodes, not the hundreds of thousands of GPUs that we will have the capability to support.

From an industry standpoint, it is incredibly exciting because, just like we’re seeing with our chip design, with AI really starting to have high-impact agentic processes coming online. I’m talking to more and more customers on broader enterprise that are seeing that impact. I think in 2026, we start to see yet more use that we all have in our day-to-day lives where AI becomes absolutely indispensable.

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Additional: Mark has his own podcast, speaking with industry luminaries. It’s worth checking out.

https://www.youtube.com/playlist?list=PLx15eYqzJiffUsiIhsSM_q-ukoW5_3YJ1

More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Arm, Armari, ASM, Ayar Labs, Baidu, Bolt Graphics, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NeuReality, NextSilicon, NordPass, NVIDIA, ProteanTecs, Qualcomm, Recogni, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.

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• CES 2026 is about platform reinforcement, not new silicon

• AMD is standardizing AI across the stack, not selling it as a premium

• Ryzen AI 400 is the real volume story

• Desktop and GPU updates are maintenance moves

• Software is where AMD is actually advancing

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NVIDIA Pays $20B for Groq License + People

Based on this post here on Groq’s website:

https://groq.com/newsroom/groq-and-nvidia-enter-non-exclusive-inference-technology-licensing-agreement-to-accelerate-ai-inference-at-global-scale

NVIDIA and Groq have entered into a non-exclusive licensing agreement whereby NVIDIA will be able to use Groq’s hardware and architecture license. On top of that, the CEO of Groq, Jonathan Ross (no, not that one, this one was on the OG TPU team), and almost everyone of note from Groq will join NVIDIA.

Groq will remain an independent company, hold the IP, and service GroqCloud (it’s online neocloud business) with all the middle-eastern deals it has done over the years.

Further disclosure over at CNBC also tells us the deal is worth $20 billion USD, NVIDIA is acquiring all of Groq’s physical assets, just not the IP.

So what on earth is going on?

Who is Groq

Groq is a company founded in 2016 that creates a product called the TSP, or Tensor Streaming Processor. It was later renamed to LPU, or Language Processing Unit, once LLMs and transformers became the flavor of the month. You might see it listed as GroqChip 1 in some documents.

This chip was released in 2019, and the CEO of the company, Jonathan Ross, hails from Google’s original TPU team. While Google’s TPU deals with large 8-way VLIW systolic arrays, the Groq chip is a large 144-way VLIW design, built at Globalfoundries, making it very cheap and easy to scale.

The downside of the chip is that it has no external DDR or HBM memory - only onboard SRAM. While fast, the 230 MB capacity per chip has been super low, and implies that a reasonably small open source model like Llama 70B requires 10 racks of processors and over 100 kW of power to run.

The upside of the chip is that it is really fast for single user inference - the architecture of the compute and the only-local memory provides some of the fastest single user token per second numbers on the market. Through its email lists, Groq has been promoting its high speed at scale for many months.

Groq were due to launch a second generation chip in 2025, with the CEO stating at a Samsung Foundry event in 2024 that there would be some revenue from its new SF4X (4nm at Samsung Foundry) design in 2025, before scaling in 2026. So far we haven’t seen evidence of this new chip in the market.

But to date, they have raised $1.8 billion dollars, including a $640m Series D in 2024 and a $750m Series E in 2025. That last one valued the company at $6.9 billion. In February 2025, Groq secured a $1.5 billion commitment from the Kingdom of Saudi Arabia for ‘expanded delivery of its advanced LPU-based AI inference infrastructure’. At that time 19,000 chips had been deployed in the region.

So what’s the $20b deal worth?

Let’s break it down into a few viewpoints.

The following is for paid subscribers only. I know most of my stuff is free for everyone, but this is breaking news worth a deeper look. If I get a chance to speak to anyone at Groq or NVIDIA about this on the record, I’ll let you know. We’ll also cover the Intel/NVIDIA 18A hubbub below the fold too.

If anyone from Groq or NVIDIA wants to speak, on or off the record, my DMs are open.
Even on Christmas.

Also for those of you subscribed to me over on YouTube, we’ll be covering this in an upcoming podcast.

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• “3D HBM” Now Feasible: Offers improved AI performance and utilization.

• But Temperature Is A Problem: HBM-on-Logic exceeds safe temperatures.

• Thermal Mitigations Are Essential: imec outlines five-ish steps to solve the issue.

• Lower Clocks: Halving the frequency provides the largest thermal relief.

• Questions on Cost …

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